iv
Figure 5-6.
Configuring the digital I/O channels as
inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Figure 5-7.
Configuring channel 0 for output bit
pattern A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Figure 5-8.
Configuring channel 0 for output bit
pattern B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Figure 6-1.
Block Diagram of IRQ Circuit . . . . . . . . . . . . . 6-11
Figure B-1.
Pin Assignments for I/O Connectors
J1 to J5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Figure B-2.
Pin Assignments for Edge Connector on
CAB-SSR Cable . . . . . . . . . . . . . . . . . . . . . . . . . B-2
List of Tables
Table 3-1.
Priorities for IRQ Levels . . . . . . . . . . . . . . . . . . 3-9
Table 6-1.
I/O Address Map for a PIO-SSR-24 . . . . . . . . . . 6-8
Table 6-2.
I/O Address Map for a PIO-SSR-48 . . . . . . . . . . 6-8
Table 6-3.
I/O Address Map for a PIO-SSR-120 . . . . . . . . . 6-9
Table 6-4.
Bit Assignments for a Control Word
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Table 6-5.
Addresses of IRQ Control Register Bits for a
PIO-SSR-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
Table 6-6.
Addresses of IRQ Control Register Bits for a
PIO-SSR-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
Table 6-7.
Addresses of IRQ Control Register Bits for a
PIO-SSR-120 . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
Table 7-1.
Troubleshooting Information . . . . . . . . . . . . . . . 7-3
Table A-1.
Digital Input/Output Specifications . . . . . . . . . . A-1
Table A-2.
Interrupt Request Specifications . . . . . . . . . . . . . A-1
Table A-3.
Input Parameter Specifications . . . . . . . . . . . . . . A-2
Table A-4.
Output Parameter Specifications . . . . . . . . . . . . A-2
Table A-5.
General Specifications . . . . . . . . . . . . . . . . . . . . A-2
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