iii
List of Figures
Figure 2-1.
Block Diagram of a PIO-SSR-24 . . . . . . . . . . . . 2-1
Figure 2-2.
Block Diagram of PIO-SSR-48 . . . . . . . . . . . . . 2-2
Figure 2-3.
Block Diagram of PIO-SSR-120 . . . . . . . . . . . . 2-3
Figure 3-1.
Switch and Jumper Locations . . . . . . . . . . . . . . . 3-6
Figure 3-2.
Base-Address Switch Values . . . . . . . . . . . . . . . 3-7
Figure 3-3.
Jumper Block for Selection of IRQ Level . . . . . 3-8
Figure 3-4.
Cable Clamp on a Mounting Plate . . . . . . . . . . 3-10
Figure 3-5.
Cabling in Place . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Figure 3-6.
Cable Clamp Securing Single Cable . . . . . . . . . 3-11
Figure 3-7.
Cabling Taped to Show Shield Boundary . . . . 3-12
Figure 3-8.
Cabling Wrapped with Jacket to
Tape Boundary . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Figure 3-9.
Jacket Trimmed with Scissors to Make
½
-Inch Flaps . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Figure 3-10. Jacket with Flaps Folded Back to Expose
Shield Surface . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Figure 3-11. Cabling Reconnected, Placing Shield Surface
in Line with Clamp . . . . . . . . . . . . . . . . . . . . . . 3-13
Figure 3-12. Detail of Clamped Cable Showing
Installed Jacket . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Figure 4-1.
Connecting an STP-50 to a PIO-SSR Series
Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Figure 4-2.
Connecting Two STP-50s to a PIO-SSR Series
Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Figure 4-3.
Connecting a PB-24 or PB-24SM to a
PIO-SSR Series Board . . . . . . . . . . . . . . . . . . . . 4-2
Figure 4-4.
Connecting Two PB-24 or PB-24SM
Accessories to a PIO-SSR Series Board . . . . . . . 4-3
Figure 4-5.
Contact-Closure Monitoring at an Input of a
PIO-SSR Series Board . . . . . . . . . . . . . . . . . . . . 4-4
Figure 4-6.
Bounce Circuit for an Input of a PIO-SSR
Series Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Figure 4-7.
NPN Transistor Relay Control for an Output
of a PIO-SSR Series Board . . . . . . . . . . . . . . . . . 4-5
Figure 5-1.
An AIO Panel example . . . . . . . . . . . . . . . . . . . . 5-2
Figure 5-2.
DIO channel tab example . . . . . . . . . . . . . . . . . . 5-3
Figure 5-3.
Configuring the digital I/O channels as inputs
and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Figure 5-4.
Configuring channel 0 for output bit
pattern A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Figure 5-5.
An AIO Panel example . . . . . . . . . . . . . . . . . . . . 5-7
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