Keithley DAS-4300 Series, User Manual, Page: 23 / 94

2-8 Functional Description
You can also use the Clk IO connector as an output. When the board is
configured for an internal pacer clock source, a TTL-level output signal is
provided on the Clk IO connector that has the same frequency as the
crystal oscillator.
External Pacer Clock
An external pacer clock is an externally generated TTL-level clock signal
of at least 100 MHz, with a duty cycle of 50/50 ±20%, applied to the
Clk IO connector. When you start an analog input operation, the board is
armed. At the next rising edge (and at every subsequent rising edge of the
external pacer clock), a conversion is initiated.
A 20
Ω
series protection resistor is provided on the clock input signal.
The 20
Ω
resistor combined with the output resistance of the driver IC (a
74ABT series TTL input with a 2 k
Ω
pull-up resistor) makes the output
appear as approximately 50
Ω
.
You can use a jumper-selectable 50
Ω
termination resistor on the clock
input signal; this resistor is particularly useful when working with a signal
driving a long line or a line that is driving many devices (where the
DAS-4301/8K is at the end of the line). Refer to page 3-18 for more
information on this jumper.
Table 2-2. Available Conversion Rates Using Internal Clock
Conversion Rate
Sample
Period
Conversion Rate
Sample
Period
1 Gsamples/s 1 ns 12.5 Msamples/s 80 ns
500 Msamples/s 2 ns 6.25 Msamples/s 160 ns
250 Msamples/s 4 ns 3.125 Msamples/s 320 ns
100 Msamples/s 10 ns 1.5625 Msamples/s 640 ns
50 Msamples/s 20 ns 0.78250 Msamples/s 1280 ns
25 Msamples/s 40 ns