Figure 4-18
Digital input, monitoring micro-switches..................................................................................................
4-17
Figure 4-19
Model 7022 card installation in Model 7001 ............................................................................................
4-18
Figure 4-20
Mating the PC-boards................................................................................................................................
4-19
Figure 4-21
Mating connector (solder-side view).........................................................................................................
4-20
5
Operation
Figure 5-1
Model 7001 channel status display..............................................................................................................
5-2
Figure 5-2
Model 7002 channel status display (slot 1) .................................................................................................
5-2
Figure 5-3
Channel display organization ......................................................................................................................
5-3
Figure 5-4
Model 7022 programming channel assignments .........................................................................................
5-3
Figure 5-5
Thick film resistor network testing..............................................................................................................
5-7
Figure 5-6
Four-terminal ohms measurements .............................................................................................................
5-8
Figure 5-7
Voltage divider checks ................................................................................................................................
5-9
Figure 5-8
Transistor testing .......................................................................................................................................
5-10
Figure 5-9
DC parameter checks.................................................................................................................................
5-11
Figure 5-10
Common-emitter characteristics of an NPN silicon transistor ..................................................................
5-12
Figure 5-11
Path isolation resistance ............................................................................................................................
5-12
Figure 5-12
Voltage attenuation by path isolation resistance .......................................................................................
5-13
Figure 5-13
Power line ground loops ............................................................................................................................
5-14
Figure 5-14
Eliminating ground loops ..........................................................................................................................
5-14
6
Service Information
Figure 6-1
Path resistance testing..................................................................................................................................
6-3
Figure 6-2
Common-mode offset current testing ..........................................................................................................
6-4
Figure 6-3
Differential offset current testing ................................................................................................................
6-5
Figure 6-4
Contact potential testing ..............................................................................................................................
6-6
Figure 6-5
Path isolation testing (guarded) ...................................................................................................................
6-7
Figure 6-6
Differential isolation testing ........................................................................................................................
6-8
Figure 6-7
Common-mode isolation testing................................................................................................................
6-10
Figure 6-8
Testing an input or output channel ............................................................................................................
6-10
Figure 6-9
Model 7022 block diagram........................................................................................................................
6-11
Figure 6-10
Start and stop sequences ............................................................................................................................
6-12
Figure 6-11
Transmit and acknowledge sequence ........................................................................................................
6-12
vi
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