XV-M52SL/XV-M50BK
1-36
Pin NO.
Symbol
I/O
Function
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
Land / group switch
Tracking ON
Serial output
L and R identification output
Clock for serial output
Interpolation flag input
Sub-code,Block clock input
L and R identification signal output
16.9MHz oscillation
16.9MHz oscillation
Terminal MASTER polarity switch input
CIRC-RAM OVER/UNDER
Interruption signal input
Sub-code, Clock output for serial input
Sub-code, Serial input
Sub-code, Frame clock input
Read clock to DAT3~0
(Output of dividing frequency four from ADSC)
Read data from DISC
(Parallel output from ADSC)
Debugging serial clock
(270 pull up)
Debugging serial data
(270 pull up)
Internal goods title monitor
Eject detection
Tray close detection
ATAPI Drive active/
Slave connection I/O
ATAPI host chip select
ATAPI host chip select
ATAPI host address
ATAPI host address
O
I
O
O
I
I
I
I
I,O
I,O
I/O
I/O
O
I
I
I
I
I
I
I/O
I/O
O
O
O
O
I
I
I/O
I
I
I/O
I/O
LG
NTRON
DACDATA
DACLRCK
DACCLK
IPFLAG
BLKCK
LRCK
VSS
OSCI1
OSCO1
VDD
PVSS
PVDD
P1
P0
VSS
SBCK
SUBC
XCLDCK
CHCK4
DAT3
DAT2
DAT1
DAT0
VDD
SCLOCK
SDATA
MONI3
MONI2
MONI1
MONI0
VSS
NEJECT
5VDD
NTRYCL
NDASP
NCS3FX
NCS1FX
VDD
DA2
DA0
MN103007BGA(3/4)
Summary of Contents for XV-M50BK
Page 88: ...XV M52SL XV M50BK 2 17 ...
