XV-M52SL/XV-M50BK
1-27
1.Terminal layout
2.Block diagram
FEP I/F
CIRC core
Standard
clock
generation
PWM
A/D converter
(Analog control)
Focus servo
Tracking servo
Traverse servo
Spindle servo
SERVO
DSP core
Serial port
CPU I/F
PLL
PLL
PLL
Detection at
FG cycle
Line speed
detection
Track crossing
counter
A/Dconverter
The signal of the error
of the servo input
from FEP.
Driver
ODC
Phase
comparison
CPU
FEP
C r y s t a l
33.8MHz
Spindre / traverse
driving value output
Focus tracking
driving value output
ADSC function block of the second generation.
MN67705
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
FGC
LDONA
LDONB
PULIN
SRF
DVSS
TRAYSET1
TRAYSET2
DRVMUTE
DVDD
TRVSW
TRAY-CLOSE
TRAY-OPEN
ST/SP
HFMON
BRK
DVSS
PLLOK
N.C.
TBAL(PWMDA1)
GBAL(PWMDA2)
BDOLVL(PWMDA3)
OFTLVL(PWMDA4)
N.C.
N.C.
N.C.
DVSS
DVDD
TSTSG
FUPDN
MONA
MONB
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
AVSS
TS(AD1)
FS(AD2)
FE(AD3)
TROFS(AD4)
TE(AD5)
VREFLDA
VREFMDA
VREFHDA
TG(AD6)
N.C.(AD7)
N.C.(AD8)
RFENV(AD9)
VREFOP
LDCUR(AD10)
JITOUT(AD11)
VREFC
AVDD(AD12)
VREFHAD
VREFMAD
VREFLAD
AVSS
DVDD
DVSS
TX
MOND
IPFLAG
CIRCIRQ
DACDATA
DACLRCK
DACCLK
DVSS
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
CPSEN
CPCEN
CPUIRQ
CPUCLK
CPUDTIN
CPUDT
OUT
CHK4I
SCLK+
SCLK-
SD
A
T
+
SD
A
T
-
BDO
SBCK
IREF2
IREF3
VCOF2
D
VSS
VCOF3
D
VSS
D
VDD
SUBC
BLKCLK
MONC
NCLDCK
LRCK
NTR
ON
D
VSS
DA
T
0
DA
T
1
DA
T
2
DA
T
3
CHCK4
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
FEPNTR
ON
N.C
.
N.C
.
CDD
VD
N.C
.
N.C
.
N.C
.
ECR(PWM3B)
EC(PWM3A)
DV
S
S
SYSCLK
VCOF1
DV
S
S
IREF1
XRESET
TEST
MINTEST
FG
DSLO
TKCRS2
TKCRS1
OFTR
D
VDD
TRSDR
VB(D
A8)
TRSDR
V
A
(D
A7)
TRDR
V(D
A6)
FODR
V(D
A5)
DBAL(D
A4)
BOOST(D
A3)
FC(D
A2)
FBAL(D
A1)
A
VDD
MN67705EA (IC201) : Digital servo controller
Summary of Contents for XV-M50BK
Page 88: ...XV M52SL XV M50BK 2 17 ...