XV-FA90BK/XV-FA92SL/XV-FA95GD
1-50
3.Pin function
1.Pin layout
NJU3715G-W(IC802) : L.E.D.Driver
2.Block diagram
DATA
CLK
STB
CLR
P1
P2
P3
P4
P5
P15
P16
Shift
resistor
Latch
circuit
Control Circuit
1~5
6
7~11
12
13
14
15
16
17
18
19~21
22
D3~D7
VSS
STLED,PONLED,PROGLED
DDPLED,ALED
DATA
CLK
ST
CLR
READY
MUTE
DCH,D1,D2
VCC
O
-
O
I
I
I
I
I
-
I
O
-
Parallel conversion data output terminal.
Connect to GND.
Parallel conversion data output terminal.
Serial data input terminal.
Clock signal input terminal.
Strobe signal input terminal.
Clear signal input terminal.
Ready signal input.
Non connect.
Muting signal input.
Parallel conversion data output terminal.
Power supply terminal.
PIN No.
I/O
Function
Symbol
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
D3
D4
D5
D6
D7
VSS
STLED
PONLED
PROGLED
DDPLED
ALED
VCC
D2
D1
DCH
MUTE
READY
CLR
STB
CLK
DATA