CMOS Setup Utility – Copyright(C) 1984-2000 Award Software
Advanced Chipset Features
Advanced DRAM Control 1 Press Enter
System BIOS Cacheable Enabled
Video RAM Cacheable Enabled
Memory Hole at 15M-16M Disabled
AGP Aperture Size 64MB
Graphic Window WR Combin Enabled
Concurrent function(MEM) Enabled
Concurrent function(PCI) Enabled
CPU Pipeline Control Enabled
PCI Delay Transaction Disabled
Memory Parity Check Disabled
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Advanced DRAM Control 1
Please refer to section 3-6-1
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result. The settings are: Enabled and Disabled.
Video RAM Cacheable
Select Enabled allows caching of the video BIOS, resulting in better system performance.
However, if any program writes to this memory area, a system error may result. The settings
are: Enabled and Disabled.
Memory Hole at 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use this area of
system memory usually discusses their memory requirements. The settings are: Enabled and
Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.
Memory Parity Check
This function provides parity check of memory.
The choice is either Disabled or Enabled.
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