SP-5000M-CXP4 / SP-5000C-CXP4
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5.3.8 Associated GenICam registers
GenICam
Name
Access
Values
Category
Line
Selector
R/W
Line1 to 11
Nand Gate 0 In1
Nand Gate 0 In2
Nand Gate 1 In1
Nand Gate 1 In2
Digital I/O Control
Line
Mode
RO
Output
Input
Digital I/O Control
Line
Inverter
R/W
False
True
Digital I/O Control
Line
Status
RO
False
True
Digital I/O Control
Line
Source
R/W
Low
High
Acquisition Trigger Wait
Acquisition Active
Frame Trigger Wait
Frame Active
Exposure Active
FVAL
PG0 to 3
User out0 to 3
TTL in
Opto1 in
CXP in (Trigger Packet)
Nand0 to 1
Line10 - TTL In 2 (Option)
Line11- LVDS In (Option)
Digital I/O Control
Line
Format
RO
TTL
LVDS
Opto
CXP
Digital I/O Control
5.4 Pulse Generator
The SP-5000-CXP4 has a frequency divider using the pixel clock as the basic clock and four pulse
generators. In each Pulse Generator, various Clear settings are connected to GPIO.
The following shows Pulse Generator default settings.
