47
Pre-defined va lues for DRAM, ca che.. timing a ccording to CPU type & system
clock.
The Choice: Ena bled, Disa bled.
Note: When this item is ena bled, the pre-defined items will become SHOW-
ONLY.
The DRAM timing is controlled by the DRAM Timing Registers. The timings
progra mmed into this register a re dependent on the system design. Slower ra tes
ma y be required in certa in system designs to support loose la youts or slower
memory.
60ns
DRAM Timing Type.
70ns
DRAM Timing Type.
DRAM must continua lly be refreshed or it will lose its da ta . Norma lly, DRAM
is refreshed entirely a s the result of a single request. This option a llows you to
determine the number of CPU clocks a lloca ted for the
R
ow
A
ddress
S
trobe to
a ccumula te its cha rge before the DRAM is refreshed. If insufficient time is
a llowed, refresh ma y be incomplete a nd da ta lost.
3
Three clocks.
4
Four clocks.
Four clocks is the default.
Auto Configuration
DRAM Timing
DRAM RAS#
Precharge Time
DRAM R/W Leadoff
Timing
