62
This sets the timing for burst mode writes from DRAM. Burst rea d a nd write
requests a re genera ted by the CPU in four sepa ra te pa rts. The first pa rt provides
the loca tion within the DRAM where the rea d or write is to ta ke pla ce while the
rema ining three pa rts provide the a ctua l da ta . The lower the timing numbers, the
fa ster the system will a ddress memory.
x222
Write DRAM timings are 2-2-2-2
x333
Write DRAM timings are 3-3-3-3
x444
Write DRAM timings are 4-4-4-4
x222 timings is the default.
The turbo read leadoff may be required in certain
system designs to support layouts or faster memories.
Disabled is the default.
The 430HX chipset is ca pa ble of a llowing a
DRAM rea d request to be genera ted slightly before the a ddress ha s been fully
decoded. This ca n reduce a ll rea d la tencies.
More simply, the CPU will issue a rea d request a nd included with this request is
the pla ce (a ddress) in m emory where the desired da ta is to be found. This request
is received by the DRAM controller. When the peculative Leadoff’ is enabled,
the controller will issue the rea d comma nd slightly before it ha s finished
determining the a ddress.
Disabled is the default.
DRAM Write Burst Timing
Turbo Read Leadoff
DRAM Speculative Leadoff
Leadoff
Summary of Contents for DP6NS
Page 5: ...5 Socket 8 Socket 8 JP9 1 1 JP11 JP4 1 JP7 JP23 Figure 2 Jumpers location...
Page 8: ...8 U SCSI Socket 8 Socket 8 U SCSI Socket 8 Socket 8 Socket 8 JP1 Socket 8 JP12...
Page 21: ...21 Socket 8 Socket 8 JP9 1 1 JP11 JP4 1 JP7 JP23 Figure 3 Jumpers for DP6NS...
Page 33: ...33 U SCSI Socket 8 Socket 8 USB SIDE USB Riser Card USB...
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