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REL 1.2

Page 23 of 56

i.MX6 SODIMM SOM Hardware User Guide

iWave Systems Technologies Pvt. Ltd.

2.6.16

I2C Interface

i.MX6 SODIMM SOM supports two I2C interface on SODIMM Edge connector. i.MX6

CPU’s I2C1

and I2C3.channels

are used for general purpose I2C interface which is compatible with the standard NXP I2C bus protocol. It supports

standard mode with data transfer rates up to 100kbps and Fast mode with data transfer rates up to 400kbps.

Since flexible I2C standard allows multiple devices to be connected to the single bus, i.MX6

CPU’s I2C1

and I2C3 can

be connected to more than one device on the carrier board. I2C1 interface is also connected to On-SOM PMIC with

I2C address 0x08 in the i.MX6 SODIMM SOM.

For more details, refer SODIMM Edge connector pins 18 & 19 for I2C1, pins 115 & 116 for I2C3 on

Table 5.

2.6.17

PWM Interface

i.MX6 SODIMM SOM supports four PWM interface on SODIMM Edge connector. i.MX6

CPU’s PWM1

PWM2, PWM3

and PWM4 module are used for PWM interface which has a 16-bit counter and optimized to generate sound from

stored sample audio images and it can also generate tones. It uses 16-bit resolution and a 4 x 16 data FIFO.

For more details, refer SODIMM Edge connector pins 125, 138, 141, & 147 on

Table 5.

2.6.18

GPIO Interface

Most of the i.MX6 CPU Pins which are connected to SODIMM Edge connector can be configured as GPIO with

interrupt capable (if not used as other interface). i.MX6 CPU GPIO controller provides dedicated general-purpose

pins that can be configured as either inputs or outputs. When configured as an output, it is possible to write to an

internal register to control the state driven on the output pin. When configured as an input, it is possible to detect

the state of the input by reading the state of an internal register. In addition, the GPIO peripheral can produce Core

interrupts.

2.6.19

JTAG Interface

i.MX6 SODIMM SOM supports one JTAG interface on SODIMM Edge Connector. i.MX6 CPU implements JTAG

Security modes internal to System JTAG Controller. The System JTAG Controller provides debug and test control with

the maximum security. The test access port is designed to support features compatible with the IEEE Standard

1149.1 v2001 (JTAG). The SJC module of the processor provides the bridge between external development and test

instrumentation and the internal JTAG-accessible debug and test resources.

For more details, refer SODIMM Edge connector pins 191, 193, 195, 197 & 199 on

Table 5.

Summary of Contents for i.MX6 SODIMM

Page 1: ...REL 1 2 Page 1 of 56 i MX6 SODIMM SOM Hardware User Guide iWave Systems Technologies Pvt Ltd iW RainboW G15M SM i MX6 SODIMM System On Module Hardware User Guide ...

Page 2: ...ection 3 3 1 is updated Table 11 Orderable Product Part Numbers are updated Non Substantive changes done throughout the document PROPRIETARY NOTICE This document contains proprietary material for the sole use of the intended recipient s Do not read this document if you are not the intended recipient Any review use distribution or disclosure by others is strictly prohibited If you are not the inten...

Page 3: ...rrata and associated issues Trademarks All registered trademarks product names mentioned in this publication are the property of their respective owners and used for identification purposes only Certification iWave Systems Technologies Pvt Ltd is an ISO 9001 2015 Certified Company Warranty RMA Warranty support for Hardware 1 Year from iWave or iWave s EMS partner For warranty terms go through the ...

Page 4: ...M PCB Edge Connector 16 2 6 1 Boot Setting 17 2 6 2 Gigabit Ethernet 18 2 6 3 PCIe Interface 18 2 6 4 SATA Interface 19 2 6 5 USB2 0 OTG Interface 19 2 6 6 USB2 0 Host Interface 19 2 6 7 SD Interface 19 2 6 8 Parallel Camera Interface 20 2 6 9 Parallel RGB Display Interface 20 2 6 10 LVDS Interface 20 2 6 11 HDMI Interface 21 2 6 12 I2S Audio Interface 21 2 6 13 UART Interface 22 2 6 14 SPI Interf...

Page 5: ...nmental Characteristics 50 3 2 1 Environmental Specification 50 3 2 2 RoHS Compliance 50 3 2 3 Electrostatic Discharge 50 3 3 Mechanical Characteristics 51 3 3 1 i MX6 SODIMM SOM Mechanical Dimensions 51 4 ORDERING INFORMATION 52 5 APPENDIX I 54 5 1 Guidelines to insert the SODIMM SOM into Carrier board 54 5 2 Guidelines to remove the SODIMM SOM from Carrier board 54 6 APPENDIX II 55 6 1 i MX6 SOD...

Page 6: ...Side View 51 Figure 7 Module Insertion Procedure 54 Figure 8 Module Removal Procedure 54 Figure 9 i MX6 SODIMM SOM Development Platform 55 List of Tables Table 1 Acronyms Abbreviations 7 Table 2 Terminology 9 Table 3 Boot Mode Pin Settings Truth Table 17 Table 4 Compatible Magnetics 18 Table 5 200 Pin PCB Edge Connector Pin Assignment 25 Table 6 IOMUX Configuration of i MX6 SODIMM SOM Edge Connect...

Page 7: ... 6mm x 37mm and provides the functional requirements for an embedded application A single ruggedized SODIMM connector provides the carrier board interface to carry all the I O signals to and from the SODIMM module 1 3 List of Acronyms The following acronyms will be used throughout this document Table 1 Acronyms Abbreviations Acronyms Abbreviations ARM Advanced RISC Machine BPP Bits Per Pixel BSP B...

Page 8: ...z Mega Hertz NC No Connect PCB Printed Circuit Board PCIe Peripheral Component Interface Express PMIC Power Management Integrated Circuit PWM Pulse Width Modulation RTC Real Time Clock SAI Synchronous Audio Interface SD Secure Digital SDRAM Synchronous Dynamic Random Access Memory SOM System On Module SODIMM Small Outline Dual in line Memory Module UART Universal Asynchronous Receiver Transmitter ...

Page 9: ...onal Input output Signal CMOS Complementary Metal Oxide Semiconductor Signal DIFF Differential Signal OD Open Drain Signal OC Open Collector Signal Power Power Pin PU Pull Up PD Pull Down NA Not Applicable NC Not Connected Note Signal Type does not include internal pull ups or pull downs implemented by the chip vendors and only includes the pull ups or pull downs implemented On SOM 1 5 References ...

Page 10: ...and CPU Pad name is SD1_DATA1 If CPU pin functionality name and pad name is different Signal name is mentioned as Functionality name CPU Pad name Example CAN1_RXD UART3_RTS_B In this signal CAN1_RXD is the functionality which we are using and UART3_RTS_B is the CPU Pad name If CPU pin functionality is GPIO Signal name is mentioned as FunctionalityDescription CPU Pad name Example PWM4_OUT GPIO1_IO0...

Page 11: ...USBOTG x 1 I2C x 2 USB OTG HS PHY USB HOST1 HS PHY MMC 8bit SPI MMDC eCSPI1 uSDHC4 I2S x 1 AUDMUX4 UART2 DISP0 SJC JTAG Power to Peripherals 3 3V Debug HDMI 1 4 PMIC RGB LCD 24bpp HDMI UART1 UART4 UART5 UART3 x 3 LVDS LVDS0 CSI0 Camera 8bit 3 1 Solo CPU supports only 32bit DDR3 interface 2 SATA interface is not supported in i MX6 Duallite and Solo CPU 3 If Parallel camera interface is used then tw...

Page 12: ... Flash Expandable 4GB eMMC Flash Expandable SODIMM PCB Edge Interfaces Boot Mode Control Signals Gigabit Ethernet through On SOM Ethernet PHY Transceiver x 1 Port PCIe x 1 Port SATA II 3 0 Gbps x 1 Port 1 USB2 0 OTG x 1 Port USB2 0 Host x 1 Port SD 4bit x 1 Port Parallel Camera Port 8bit x 1 Port 2 3 Parallel RGB Display 24bpp x 1 Port 4 LVDS x 1 Port 4 HDMI 1 4 x 1 Port 4 I2S Audio Interface x 1 ...

Page 13: ... Solo CPU 2 If Parallel camera interface is used then two data UART interfaces UART4 UART5 cannot be used with hardware flow control signals on SODIMM edge 3 If Parallel camera is used with 12bit interface then SPI interface eCSPI2 cannot be used on SODIMM edge 4 i MX6 Duallite and i MX6 Solo CPU supports only one IPU and so at any time only two display interfaces including LVDS HDMI Parallel RGB ...

Page 14: ...s up to 1 2 GHz i MX6 CPU is NXP s latest achievement in integrated multimedia application processors which is part of growing multimedia focused products that offers high performance processing and are optimized for lowest power consumption The Block Diagram of i MX6 CPU from the NXP s i MX6 Quad Dual datasheet is shown below for reference Figure 2 i MX6 Simplified Block Diagram Note Please refer...

Page 15: ...MB DDR3 SDRAM ICs These devices operate at 1 5V voltage level Each pair of DDR3 ICs is physically located on either side of the iMX6 SODIMM SOM The RAM size can be expandable up to maximum of 4GB Note By default 512MB DDR3 with 32bit mode only supported in i MX6 Solo CPU based SODIMM SOM 2 5 2 SPI NOR Flash The i MX6 SODIMM SOM supports 2MB SPI NOR Flash as default boot device This is connected to...

Page 16: ...orts JEDEC Physical Standard 200pin SODIMM PCB edge connector for interfaces expansion The interfaces which are available at SODIMM Edge connector are explained in the following sections Figure 3 i MX6 SODIMM PCB Edge Connector Number of Pins 200 Connector Part Not Applicable On Board PCB Edge connector Mating Connector 1473005 1 from TE Connectivity ...

Page 17: ... These Boot mode selection signals are connected to SODIMM Edge connector and desired boot mode must be set from the carrier board as explained in the below table For more details refer SODIMM Edge connector pins 182 184 on Table 5 Table 3 Boot Mode Pin Settings Truth Table BOOT_MODE 1 SODIMM Edge Pin 184 BOOT_MODE 0 SODIMM Edge Pin 182 Boot Type Description 1 0 Internal Boot Mode In this mode i M...

Page 18: ... HX5008NL Pulse 40 C to 85 C RJ45 Magjack with two Green LED JK0654219NL Pulse 0 C to 70 C RJ45 Magjack with two Green LED 0826 1G1T 23F Bel Fuse 0 C to 70 C Gigabit Ethernet Discrete Transformer 000 7093 37R LF1 Wurth 0 C to 70 C For more details refer SODIMM Edge connector pins 2 4 6 8 14 16 15 17 on Table 5 Note As per i MX6 CPU Errata ERR004512 Gigabit Ethernet MAC has throughout limitation Th...

Page 19: ... Table 5 2 6 6 USB2 0 Host Interface i MX6 SODIMM SOM supports one USB2 0 Host interface on SODIMM Edge connector i MX6 CPU s USB2 0 Host controller core with integrated PHY is used for USB2 0 Host interface which can operate in High Speed operation 480 Mbps Full Speed operation 12Mbps and Low Speed operation 1 5 Mbps For more details refer SODIMM Edge connector pins 39 140 188 190 on Table 5 2 6 ...

Page 20: ...display interface which supports upto 24bit data bus 8bits colour i MX6 CPU s LCD can support data rate up to up to 225 Mpixels sec for example WUXGA at 60 Hz or dual HD1080 and WXGA at 60 Hz For more details refer SODIMM Edge Connector pins 143 144 145 146 148 149 150 152 153 154 155 156 157 158 159 161 162 163 164 165 166 167 168 170 171 172 173 174 on Table 5 Note i MX6 Duallite and i MX6 Solo ...

Page 21: ...e level shifter and driver to interface the I2C with the HDMI monitor since i MX6 CPU s I2C cannot operate at the 5 V required by HDMI EDID In addition ESD protection must be used on all HDMI single ended and differential signals mounted near the HDMI connector CM2020 from ON semiconductor or similar part could be considered for ESD protection and I2C level conversion For more details refer SODIMM...

Page 22: ... be used with hardware flow control for request to send and clear to send signals 2 6 14SPI Interface i MX6 SODIMM SOM supports one SPI interface with three chip selects on SODIMM Edge connector i MX6 CPU s eCSPI2 is used for SPI interface which supports full duplex synchronous four wire serial interface with DMA It supports 32bit x 64 entry FIFO for both transmit and receive data It can be config...

Page 23: ...solution and a 4 x 16 data FIFO For more details refer SODIMM Edge connector pins 125 138 141 147 on Table 5 2 6 18GPIO Interface Most of the i MX6 CPU Pins which are connected to SODIMM Edge connector can be configured as GPIO with interrupt capable if not used as other interface i MX6 CPU GPIO controller provides dedicated general purpose pins that can be configured as either inputs or outputs W...

Page 24: ...POR pin in i MX6 SODIMM SOM This pin can be used to reset the i MX6 CPU by connecting push button in the carrier board For more details refer SODIMM Edge connector pin 187 on Table 5 2 6 22Power Button Input i MX6 SODIMM SOM supports PWRBTN input from Edge connector which is the active low signal and connected to i MX6 CPU s ONOFF pin This pin can be used to On Off the i MX6 CPU by connecting push...

Page 25: ...s LED 12 GPHY_ACTIVITY_LED1 NA O 3 3V CMOS Ethernet speed status LED 13 GND NA Power Ground 14 GPHY_CTXRXM NA IO DIFF Ethernet receive differential pair 2 negative 15 GPHY_DTXRXM NA IO DIFF Ethernet receive differential pair 3 negative 16 GPHY_CTXRXP NA IO DIFF Ethernet receive differential pair 2 positive 17 GPHY_DTXRXP NA IO DIFF Ethernet receive differential pair 3 positive 18 I2C1_SCL EIM_D21 ...

Page 26: ...1 NANDF_CS0 NANDF_CS0 F15 IO 3 3V CMOS General Purpose Input Output 37 GPIO2_IO02 NANDF_D2 NANDF_D2 F16 IO 3 3V CMOS General Purpose Input Output 38 UART5_RTS_B CSI0_DAT18 CSI0_DAT18 M6 I 3 3V CMOS Parallel camera data 6 39 USB_H1_OC EIM_D30 EIM_D30 J20 I 3 3V CMOS Over current sense for USB Host Port 1 40 GND NA Power Ground 41 GND NA Power Ground 42 GPIO1_IO20 SD1_CLK SD1_CLK D20 IO 3 3V CMOS Ge...

Page 27: ... 57 LVDS0_CLK_N LVDS0_CLK_N V4 O 2 5V LVDS LVDS primary channel differential clock negative 58 LVDS0_TX3_P LVDS0_TX3_P W1 O 2 5V LVDS LVDS primary channel differential pair 3 positive 59 LVDS0_CLK_P LVDS0_CLK_P V3 O 2 5V LVDS LVDS primary channel differential clock positive 60 VIN_3V3 NA I 3 3V Power Supply Voltage 61 AUD4_RXD SD2_DAT0 SD2_DAT0 A22 I 3 3V CMOS Audio receive data 62 eCSPI2_SS1 EIM_...

Page 28: ...F_D5 B18 IO 3 3V CMOS General Purpose Input Output 77 USBOTG_ID GPIO_1 GPIO_1 T4 I 3 3V CMOS USB OTG ID to identify Host Device 78 GPIO2_IO07 NANDF_D7 NANDF_D7 C18 IO 3 3V CMOS General Purpose Input Output 79 GND NA Power Ground 80 GPIO4_IO20 DI0_PIN4 DI0_PIN4 P25 IO 3 3V CMOS General Purpose Input Output 81 USB_OTG_DP USB_OTG_DP A6 IO DIFF USB OTG data positive 82 SATA_TXP SATA_TXP A12 O DIFF 0 0...

Page 29: ... EIM_D19 EIM_D19 G21 O 3 3V CMOS UART1 clear to send data 98 UART4_TXD KEY_COL0 KEY_COL0 W5 O 3 3V CMOS UART4 serial data transmitter 99 UART4_RXD KEY_ROW0 KEY_ROW0 V6 I 3 3V CMOS UART4 serial data receiver 100 UART4_CTS_B CSI0_DAT17 CSI0_DAT17 L3 I 3 3V CMOS Parallel camera0 data 5 101 UART4_RTS_B CSI0_DAT16 CSI0_DAT16 L4 I 3 3V CMOS Parallel camera0 data 4 102 UART5_TXD KEY_COL1 KEY_COL1 U7 O 3 ...

Page 30: ...CMOS Parallel camera0 PIXCLK 120 GPIO5_IO30 CSI0_DAT12 CSI0_DAT12 M2 I 3 3V CMOS Parallel camera0 data 0 121 GPIO5_IO21 CSI0_VSYNC CSI0_VSYNC N2 I 3 3V CMOS Parallel camera0 VSYNC 122 GPIO7_IO13 GPIO_18 GPIO_18 P6 IO 3 3V CMOS General Purpose Input Output 123 GPIO5_IO19 CSI0_MCLK CSI0_MCLK P4 I 3 3V CMOS Parallel Camera0 HSYNC 124 VIN_3V3 NA I 3 3V Power Supply Voltage 125 PWM2_OUT SD1_DAT2 SD1_DA...

Page 31: ... 139 GPIO4_IO12 KEY_COL3 KEY_COL3 U5 IO 3 3V CMOS General Purpose Input Output 140 USB_H1_PWR GPIO_0 GPIO_0 T5 O 3 3V CMOS General Purpose Input Output Assigned for USB Host1 Power enable signal to control USB Host1 VBUS voltage 141 PWM4_OUT SD1_CMD SD1_CMD B21 O 3 3V CMOS Pulse Width Modulation 4 Output 142 VIN_3V3 NA I 3 3V Power Supply Voltage 143 DI0_PIN3 DI0_PIN3 N20 O 3 3V CMOS Parallel LCD ...

Page 32: ...1 DISP0_DAT11 T23 O 3 3V CMOS Parallel LCD data 11 Green data3 162 DISP0_DAT12 DISP0_DAT12 T24 O 3 3V CMOS Parallel LCD data 12 Green data4 163 DISP0_DAT13 DISP0_DAT13 R20 O 3 3V CMOS Parallel LCD data 13 Green data5 164 DISP0_DAT14 DISP0_DAT14 U25 O 3 3V CMOS Parallel LCD data 14 Green data6 165 DISP0_DAT15 DISP0_DAT15 T22 O 3 3V CMOS Parallel LCD data 15 Green data7 166 DISP0_DAT0 DISP0_DAT0 P24...

Page 33: ... populated CPU_ON_OFF is also connected to Edge connector pin196 through resistor and default populated 180 VIN_3V3 NA I 3 3V Power Supply Voltage 181 GPIO4_IO11 KEY_ROW2 KEY_ROW2 W4 IO 3V CMOS General Purpose Input Output 182 BOOT_MODE0 BOOT_MODE0 C12 I 3 3V CMOS 4 7K PU Boot Mode Select bit0 Important Note This pin is directly connected to i MX6 CPU s BOOT_MODE0 pin with On SOM pullup and so don...

Page 34: ...FF USB Host Port 1 data negative 191 JTAG_TDO JTAG_TDO G6 O 3 3V CMOS JTAG Test Data Output 192 VIN_3V3 NA I 3 3V Power Supply Voltage 193 JTAG_TRSTB JTAG_TRSTB C2 I 3 3V CMOS JTAG Test Reset 194 GPIO1_IO05_BRD_CFG3 GPI O_5 GPIO_5 R4 IO 3 3V CMOS General Purpose Input Output Note GPIO_5 is connected to this pin through resistor and default populated 195 JTAG_TDI JTAG_TDI G5 I 3 3V CMOS JTAG Test D...

Page 35: ... Edge Connector Pin Name i MX6 Ball Name Pin Number Signal Type Termination Description 199 JTAG_TMS JTAG_TMS C3 I 3 3V CMOS JTAG Test Mode Select 200 VBUS_5V USB_OTG_VBUS E9 USB_H1_VBUS D10 I Power 5V USB VBUS Power Important Note Recommended to connect always available 5V power on this pin in carrier board ...

Page 36: ...nnector for iWave s BSP reusability and to have compatible SODIMM modules in future for upgradability Table 6 IOMUX Configuration of i MX6 SODIMM SOM Edge Connector interfaces Interface Function SODIMM Edge Pin No i MX6 CPU Pad Name ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9 Default Reset State Control Signals 182 BOOT_MOD E0 SRC_BOOT_ MODE0 184 BOOT_MOD E1 SRC_BOOT_ MODE1 187 POR_B SRC_POR...

Page 37: ...LK1_P XTALOSC_CL K1_P 137 CLK1_N XTALOSC_CL K1_N 134 GPIO_2 ESAI_TX_FS KEY_ROW6 GPIO1_IO02 SD2_WP MLB_DATA GPIO1_IO02 133 GPIO_17 ESAI_TX0 ENET_1588_ EVENT3_IN CCM_PMIC_ READY SDMA_EXT_ EVENT0 SPDIF_OUT GPIO7_IO12 GPIO7_IO12 SATA 82 SATA_TXP SATA_PHY_T X_P 84 SATA_TXM SATA_PHY_T X_N 85 SATA_RXP SATA_PHY_R X_P 87 SATA_RXM ATA_PHY_RX _N USB OTG2 0 74 USB_OTG_C HD_B USB_OTG_C HD_B 77 GPIO_1 ESAI_RX_C...

Page 38: ...O31 ARM_TRACE 10 GPIO5_IO31 96 CSI0_DAT14 IPU1_CSI0_D ATA14 EIM_DATA1 0 UART5_TX_ DATA GPIO6_IO00 ARM_TRACE 11 GPIO6_IO00 93 CSI0_DAT15 IPU1_CSI0_D ATA15 EIM_DATA1 1 UART5_RX_ DATA GPIO6_IO01 ARM_TRACE 12 GPIO6_IO01 101 CSI0_DAT16 IPU1_CSI0_D ATA16 EIM_DATA1 2 UART4_RTS_ B GPIO6_IO02 ARM_TRACE 13 GPIO6_IO02 100 CSI0_DAT17 IPU1_CSI0_D ATA17 EIM_DATA1 3 UART4_CTS_ B GPIO6_IO03 ARM_TRACE 14 GPIO6_IO0...

Page 39: ..._DAT2 SD2_DATA2 ECSPI5_SS1 EIM_CS3_B AUD4_TXD KEY_ROW6 GPIO1_IO13 GPIO1_IO13 90 SD2_DAT3 SD2_DATA3 ECSPI5_SS3 KEY_COL6 AUD4_TXC GPIO1_IO12 GPIO1_IO12 91 SD2_CMD SD2_CMD ECSPI5_MOS I KEY_ROW5 AUD4_RXC GPIO1_IO11 GPIO1_IO11 92 SD2_CLK SD2_CLK ECSPI5_SCLK KEY_COL5 AUD4_RXFS GPIO1_IO10 GPIO1_IO10 LVDS 50 LVDS0_TX0_ P LVDS0_DATA 0_P 48 LVDS0_TX0_ N LVDS0_DATA 0_N 54 LVDS0_TX1_ P LVDS0_DATA 1_P 52 LVDS0...

Page 40: ...0_DAT6 IPU1_DISP0_ DATA06 IPU2_DISP0_ DATA06 ECSPI3_SS3 AUD6_RXC GPIO4_IO27 GPIO4_IO27 174 DISP0_DAT7 IPU1_DISP0_ DATA07 IPU2_DISP0_ DATA07 ECSPI3_RDY GPIO4_IO28 GPIO4_IO28 157 DISP0_DAT8 IPU1_DISP0_ DATA08 IPU2_DISP0_ DATA08 PWM1_OUT WDOG1_B GPIO4_IO29 GPIO4_IO29 158 DISP0_DAT9 IPU1_DISP0_ DATA09 IPU2_DISP0_ DATA09 PWM2_OUT WDOG2_B GPIO4_IO30 GPIO4_IO30 159 DISP0_DAT1 0 IPU1_DISP0_ DATA10 IPU2_DI...

Page 41: ...D AUD4_RXC GPIO5_IO13 EIM_CS3_B GPIO5_IO13 153 DISP0_DAT2 0 IPU1_DISP0_ DATA20 IPU2_DISP0_ DATA20 ECSPI1_SCLK AUD4_TXC GPIO5_IO14 GPIO5_IO14 154 DISP0_DAT2 1 IPU1_DISP0_ DATA21 IPU2_DISP0_ DATA21 ECSPI1_MOS I AUD4_TXD GPIO5_IO15 GPIO5_IO15 155 DISP0_DAT2 2 IPU1_DISP0_ DATA22 IPU2_DISP0_ DATA22 ECSPI1_MIS O AUD4_TXFS GPIO5_IO16 GPIO5_IO16 156 DISP0_DAT2 3 IPU1_DISP0_ DATA23 IPU2_DISP0_ DATA23 ECSPI...

Page 42: ...HPD HDMI_TX_H PD SPI 66 CSI0_DAT8 IPU1_CSI0_D ATA08 EIM_DATA0 6 ECSPI2_SCLK KEY_COL7 I2C1_SDA GPIO5_IO26 ARM_TRACE 05 GPIO5_IO26 70 CSI0_DAT9 IPU1_CSI0_D ATA09 EIM_DATA0 7 ECSPI2_MOS I KEY_ROW7 I2C1_SCL GPIO5_IO27 ARM_TRACE 06 GPIO5_IO27 63 CSI0_DAT10 IPU1_CSI0_D ATA10 AUD3_RXC ECSPI2_MIS O UART1_TX_ DATA GPIO5_IO28 ARM_TRACE 07 GPIO5_IO28 110 CSI0_DAT11 IPU1_CSI0_D ATA11 AUD3_RXFS ECSPI2_SS0 UART...

Page 43: ...5_TXC KEY_COL0 UART4_TX_ DATA GPIO4_IO06 DCIC1_OUT GPIO4_IO06 99 KEY_ROW0 ECSPI1_MOS I ENET_TX_DA TA3 AUD5_TXD KEY_ROW0 UART4_RX_ DATA GPIO4_IO07 DCIC2_OUT GPIO4_IO07 UART5 102 KEY_COL1 ECSPI1_MIS O ENET_MDIO AUD5_TXFS KEY_COL1 UART5_TX_ DATA GPIO4_IO08 SD1_VSELEC T GPIO4_IO08 103 KEY_ROW1 ECSPI1_SS0 ENET_COL AUD5_RXD KEY_ROW1 UART5_RX_ DATA GPIO4_IO09 SD2_VSELEC T GPIO4_IO09 I2C1 19 EIM_D28 EIM_D...

Page 44: ...X IPU1_SISG4 USB_OTG_O C KEY_COL4 UART5_RTS_ B GPIO4_IO14 GPIO4_IO14 PWM 138 GPIO_9 ESAI_RX_FS WDOG1_B KEY_COL6 CCM_REF_E N_B PWM1_OUT GPIO1_IO09 SD1_WP GPIO1_IO09 125 SD1_DAT2 SD1_DATA2 ECSPI5_SS1 GPT_COMPA RE2 PWM2_OUT WDOG1_B GPIO1_IO19 WDOG1_RES ET_B_DEB GPIO1_IO19 147 SD1_DAT1 SD1_DATA1 ECSPI5_SS0 PWM3_OUT GPT_CAPTU RE2 GPIO1_IO17 GPIO1_IO17 141 SD1_CMD SD1_CMD ECSPI5_MOS I PWM4_OUT GPT_COMPA...

Page 45: ... SD4_RESET GPIO6_IO08 GPIO6_IO08 49 NANDF_D1 NAND_DATA 01 SD1_DATA5 GPIO2_IO01 GPIO2_IO01 69 NANDF_CS1 NAND_CE1_ B SD4_VSELEC T SD3_VSELEC T GPIO6_IO14 GPIO6_IO14 73 NANDF_D0 NAND_DATA 00 SD1_DATA4 GPIO2_IO00 GPIO2_IO00 122 GPIO_18 ESAI_TX1 ENET_RX_CL K SD3_VSELEC T SDMA_EXT_ EVENT1 ASRC_EXT_C LK GPIO7_IO13 SNVS_VIO_5 _CTL GPIO7_IO13 10 SD1_DAT3 SD1_DATA3 ECSPI5_SS2 GPT_COMPA RE3 PWM1_OUT WDOG2_B ...

Page 46: ...PIO6_IO31 132 GPIO_16 ESAI_TX3_RX 2 ENET_1588_ EVENT2_IN ENET_REF_C LK SD1_LCTL SPDIF_IN GPIO7_IO11 I2C3_SDA JTAG_DE_B GPIO7_IO11 136 KEY_ROW3 XTALOSC_OS C32K_32K_ OUT ASRC_EXT_C LK HDMI_TX_D DC_SDA KEY_ROW3 I2C2_SDA GPIO4_IO13 SD1_VSELEC T GPIO4_IO13 139 KEY_COL3 ECSPI1_SS3 ENET_CRS HDMI_TX_D DC_SCL KEY_COL3 I2C2_SCL GPIO4_IO12 SPDIF_IN GPIO4_IO12 179 KEY_COL2 ECSPI1_SS1 ENET_RX_D ATA2 FLEXCAN1_T...

Page 47: ...IMM SOM Table 7 Power Input Requirement Sl No Power Rail Min V Typical V Max V Max Input Ripple 1 VIN_3V3 3 15 3 3 3 45 50mV 2 VRTC_3V02 2 8 3 3 3 20 mV 3 VBUS_5V 4 4 5 5 25 50mV i MX6 SODIMM SOM is designed to work with VIN_3V3 input power rail from SODIMM Edge connector i MX6 SODIMM SOM uses this voltage as backup power source to RTC when VIN_3V3 is off This is an optional power and required onl...

Page 48: ...me time or before VRTC_3V0 goes down Figure 4 i MX6 SODIMM SOM Power Sequence Note VBUS_5V is not part of the power supply sequence and can be powered at any time Table 8 Power Sequence Timing Item Description Value T1 VRTC_3V0 rise time to VIN_3V3 rise time 0 ms T2 VIN_3V3 fall time to VRTC_3V0 fall time 0 ms Important Note All the carrier board power supplies should be powered ON only after the ...

Page 49: ...e dry2 application on back ground Powermeasurement2 sh Run the Graphics OpenGL application tiger on LVDS VIN_3V3 1 18 3 894 All above with below mentioned one change HDMI Run the VGA video akiyo mp4 on HDMI using VPU Decoder library VIN_3V3 1 09 3 597 Low Power Mode Power Consumption System Idle Mode VIN_3V3 0 2 0 66 Deep Sleep Mode VIN_3V3 0 05 0 165 User Idle Mode Enable the Bus frequency VIN_3V...

Page 50: ...carrier board and its components system enclosure air circulation in the system system power supply etc Based on the system design specific heat dissipating approach might be required from system to system It is recommended to do the necessary system level thermal simulation and find necessary thermal solution in the system before using this board in the end application 3 2 2 RoHS Compliance iWave...

Page 51: ...cal standard DDR SODIMM specification for SODIMM Edge connector mechanical details Figure 5 Mechanical dimension of i MX6 SODIMM SOM Top View i MX6 SODIMM SOM PCB thickness is 1 0 1mm top side maximum height component is SPI flash 2 16mm followed by iMX6 CPU 2 10mm and bottom side maximum height component is Capacitor 1 25mm followed by DDR3 SDRAM 1 0mm Please refer the below figure which gives he...

Page 52: ... MX6 Quad Core CPU 1GB RAM 4GB eMMC with Linux Industrial iW G15M SM04 3D001G E004G AIC i MX6 Quad Core CPU 1GB RAM 4GB eMMC with Android Industrial iW G15M SM04 3D001G E004G BIC i MX6 Quad Core CPU 1GB RAM 4GB eMMC with Boot code Industrial i MX6 Dual CPU based SODIMM SOMs iW G15M SM02 3D001G E004G LCC i MX6 Dual Core CPU 1GB RAM 4GB eMMC with Linux Commercial iW G15M SM02 3D001G E004G ACC i MX6 ...

Page 53: ...mmercial iW G15M SM01 3D512M E004G ACC i MX6 Solo Core CPU 512MB RAM 4GB eMMC with Android Commercial iW G15M SM01 3D512M E004G BCC i MX6 Solo Core CPU 512MB RAM 4GB eMMC with Boot code Commercial iW G15M SM01 3D512M E004G LIC i MX6 Solo Core CPU 512MB RAM 4GB eMMC with Linux Industrial iW G15M SM01 3D512M E004G AIC i MX6 Solo Core CPU 512MB RAM 4GB eMMC with Android Industrial iW G15M SM01 3D512M...

Page 54: ...ou feel it slip down into the socket With the module properly seated in the socket rotate the module downward as indicated in the illustration Continue pressing downward until the clips at each end of the socket lock into position Once the module has been installed Carrier board can be Powered ON with 5V power supply Figure 7 Module Insertion Procedure 5 2 Guidelines to remove the SODIMM SOM from ...

Page 55: ...arrier board for complete validation of i MX6 SODIMM SOM functionality with complete BSP support Being a Pico ITX form factor with 100mmx72mm size the i MX6 SODIMM Development Platform carrier board is highly packed with all the necessary on board connectors to validate the i MX6 CPU features with optional 4 3 resistive display kit For more details on i MX6 SODIMM SOM Development platform visit th...

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