REL 1.2
Page 20 of 82
i.MX6 Qseven PMIC SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.7.1
PCIe Interface
i.MX6 Qseven PMIC SOM supports one PCI Express Gen2.0 lane on Qseven Edge connector. i.MX6 CPU’s PCIe Express
core with integrated PHY is used for PCIe Interface which can support PCIe Gen2.0 at 5Gbps data rate and are
backward compatible to Gen1.1 at 2.5Gbps data rate. i.MX6 CPU’s PCIe PHY output is connected to Qseven Edge
connector PCIe channel 0. i.MX6 CPU’s CLK1 differential output is connected to Qseven Edge for PCIe reference
clock. Also PCIe wake input and PCIe reset output are supported on Qseven Edge connector from i.MX6 CPU GPIOs
GPIO2_6 & GPIO2_7 correspondingly.
For more details, refer Qseven Edge connector pins 155,156,157,158,179,180,181 & 182 on
Note: Termination is required on the PCIe differential clock lines and should be placed as close as possible to the
receiver device input or PCIe connector. Connect two 49.9 Ω resistors between REFCLK- and GND & and
GND. Alternately, Connect a 100 Ω resistor between REFCLK- and . PCIe differential transmitter lines are ac
coupled on SOM itself. For more details refer, i.MX6 Hardware Development Guide and Qseven design Guide.
2.7.2
Data UART Interface (UART5)
i.MX6 Qseven PMIC SOM supports one Data UART interface on Qseven Edge connector along with two more on
Expansion connector1 and one more on Expansion connector2. i.MX6 CPU’s UART5 controller is used for Data UART
interface on Qseven Edge connector which supports Serial RS-232NRZ mode, 9-bit RS-485 mode and IrDA mode. It is
compatible with High-speed TIA/EIA-232-F (up to 5.0 Mbit/s) with auto baud rate detection (up to 115.2 Kbit/s). It
supports 7 or 8 data bits for RS-232 characters (9 bit RS-485 format), 1 or 2 stop bits and programmable parity (even,
odd, and no parity). Also i.MX6 Qseven PMIC SOM supports hardware flow control for RTS and CTS signals.
For more details, refer Qseven Edge connector pins 171,172,177 & 178 on
2.7.3
Gigabit Ethernet Interface
i.MX6 Qseven PMIC SOM supports one 10/100/1000 Mbps Ethernet interface on Qseven Edge connector. The MAC
is integrated in the i.MX6 CPU and connected to the external Gigabit Ethernet PHY on SOM. Since MAC and PHY are
supported on SOM itself, only Magnetics are required on the carrier board. i.MX6 Qseven PMIC SOM also supports
Link and Activity indication LED control signals to Qseven Edge.
i.MX6 Qseven PMIC SOM supports “KSZ9031RNXI” Ethernet PHY from Micrel. This PHY is interfaced with i.MX6 CPU
using RGMII interface and works at 1.8V IO voltage level. Since this PHY doesn’t require center tap supply to the
magnetics, CTREF voltage to Qseven Edge is not supported on SOM. It is recommended that center tap pins of
magnetics should be separated from one another and connected through separate 0.1uF common mode capacitors
to ground. The below table provides some of the compatible magnetics recommended by PHY Manufacturer.
