2
January 24, 2005
ISL5585
W68131
CLOCK GENERATION
JP1 JP2
JP4
JP5
JP7
JP8
JP9
JP10
JP11
JP12
J1
J2 - Ring
J3 - Tip
J4 - Gnd
J5
J6
J9-Vrs
J10
J13
J14
J7- Vtx
J8-Vrx
J11
J12
J15
S1
S2
S3
S4
S5
S6
FIGURE 1. EVALUATION BOARD LAYOUT
HC55185
RSLIC
W6810
CODEC
JP15
DT
DR
FS
CLK
PD
A-law
JP13
F2
F1
F0
E0 SWC BSEL
LOGIC 1
LOGIC 0
ALM
LED
DET
LED
2.048 MHz
INT
OLE
5V
3.3
V
5V
3.3
V
5V
3.
3
V
Rx Gain
Tx Gain Hybrid Gain
SW+ SW-
Ring
Signal
Source
CODEC
Ext.
Trap.
POWER
512 KHz
256 KHz
CODEC Rx
POWER
PCM I/O
RSLIC Logic I/O
DRIN
DROUT
TABLE 1. EVALUATION BOARD JUMPER DEFINITIONS
JUMPER
DESCRIPTION
JP1
Connects SW- directly to the RSLIC Ring terminal. Used in conjunction with external load D
TA
and R
TA
.
JP2
Connects the SW+ D
TA
diode + R
TA
resistor load to the RSLIC Tip terminal.
JP4
Connects the receive output of the CODEC (U6) to the RSLIC receive input (VRX). Path is AC coupled with C
RX
.
JP5
Position1, CODEC: Connects the CODEC receive output to the device ringing input. Path is AC coupled by C
RS
.
Position 2, EXT: Connects the VRS connector J9 to the device ringing input. Path is AC coupled by C
RS
.
Position 3 TRAP: Connects the VRS connector J9 thru RC network to the device ringing input. Path is AC coupled.
JP7
Selects the 5V or 3.3V chip-set Hybrid Gain of the CODEC, AC coupled by C
1
.
JP8
Inserting jumper sets the CODEC to A-law coding. Open sets the CODEC to
µ
-law coding.
JP9
Inserting jumper powers down the CODEC. Open provides normal CODEC operation.
JP10
Position 1: Sets the CODEC master clock to 2.048MHz when the internal clock generator is used.
Position 2: Sets the CODEC master clock to 512kHz when the internal clock generator is used.
Position 3: Sets the CODEC master clock to 256kHz when the internal clock generator is used.
JP11
Enables the on board clock generator. Should be installed for single board or back to back evaluations when no external clock
generation is available. Remove when driving BNCs J10 thru J13 with PCM4 or other PCM interface with external CLK.
JP12
Inserting jumper selects on board clock and frame sync generator. Insert to configure board as master for back to back
evaluations or for single board evaluations. Remove to configure board as slave for back to back evaluations.
JP13
Selects Rx Gain for 5V or 3.3V RSLIC/CODEC chip-set.
JP15
Selects Tx Gain for 5V or 3.3V RSLIC/CODEC chip-set.
Application Note 1168
