7
January 24, 2005
Half-channel A-D and D-A PCM4 Testing
Description
The evaluation board is designed for 0dB gain, PCM to 2W
(D-A, Rx) and 2W to PCM (A-D, Tx) transmission paths.
These gains are established by the RSLIC gain resistor
values on the evaluation board. The CODEC D-A and A-D
gains are fixed to the values defined in the specific CODEC
data sheet. A detailed description of the AC Transmission
gain paths and equations is provided in Section 3.
The PCM4 configuration verifies the AC A-D and D-A
transmission of the 5V or 3.3V RSLIC/CODEC chip-set. Any
piece of test equipment capable of PCM testing with digital
and analog interfaces can be used in this configuration.
Jumper Settings
All jumper settings and functions are described below. All
other jumpers should be removed.
Clock and Frame Sync
The clock and frame sync signals are driven at connectors
J13 and J12 respectively. The clock input is common to the
MCLK, BCLKT and BCLKR of the CODEC. The frame sync
input is common to the receive and transmit frame syncs,
FSR and FST, of the CODEC. These connections define
synchronous mode of operation.
Digital to Analog
The receive signal path is defined from the CODEC PCM
input to the RSLIC 2W Tip and Ring outputs. The PCM4 tester
is capable of driving digital test signals on the PCM bus and
measuring the resultant analog signal at Tip and Ring. Typical
performance measurements include overall loss, gain
variation versus frequency, gain versus signal level, THD and
2-wire return loss. In addition, fidelity measurements such as
idle channel noise and distortion may also be measured.
Analog to Digital
The transmit signal path is defined from RSLIC 2W Tip and
Ring interface to the CODEC PCM output. The same tests
performed for the receive path also apply to the transmit
path.
Digital to Digital
The digital to digital path is from the CODEC PCM input to
the CODEC PCM output. This signal path provides a
measure of the trans-hybrid balance for the line circuit with a
600
Ω
termination at Tip and Ring.
Digital Loop Back Configuration
Description
The digital loop back configuration can be used to verify the
interface and operation of the RSLIC/CODEC chip-set. This
configuration provides a convenient self -test in the Forward
or Reverse active states to verify proper operation of the
analog and digital functions of the line circuit. The on-board
clock generator eliminates the need for an external PCM4
digital interface, enabling testing with a signal generator, AC
voltmeter and scope.
NOTE: Operation of the clock oscillator and logic may be
marginal at VCC less than 3.3V.
TABLE 8. INDIVIDUAL TESTS OF THE RSLIC AND THE CODEC AC GAIN PATHS
RSLIC AC Testing - Jumper Selection (All jumpers removed except as indicated)
AC Test
Install Jumpers
AC Signal Input
AC Signal Output
Measurement Results and Remarks
G
42
None
0dB at VREC
Tip to Ring
Measured value per design tables A1 or B1
G
44
None
0dB at VREC
VXMIT
Insert 600
Ω
termination resistor from Tip to Ring;
Measured value per design tables A1 or B1
G
24
None
0dB at Tip/ring
VXMIT
Signal generator source impedance = 600
Ω;
Measured value per design tables A1 or B1
CODEC AC Testing - Jumper Selection (All jumpers removed except as indicated)
Tx to PCM
JP8
JP5(3.3V or 5V)
VMXIT
Remove RSLIC to prevent input loading; Measured
value per CODEC data sheet
PCM to Rx
JP4, JP8
PCM Tx digital input
VREC
Measured value per CODEC data sheet
TABLE 9. A-D AND D-A TEST JUMPER POSITIONS
JUMPER
DESCRIPTION
JP4
Connects the receive output of the CODEC (U6) to
the RSLIC receive input VRX. Signal path is AC
coupled.
JP8
Inserting jumper set the CODEC to A-law coding.
Open sets the CODEC to
µ
-law coding. This must
match PCM test equipment coding scheme for
proper operation.
JP13
Selects Rx Gain for 5V or 3.3V RSLIC/CODEC
chip-set.
JP15
Selects Tx Gain for 5V or 3.3V RSLIC/CODEC
chip-set.
JP7
Selects the 5V or 3.3V chip-set Hybrid Gain of the
CODEC, AC coupled by C
1
.
Application Note 1168
