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January 24, 2005

CODEC Measurement Set-up

Test access to the CODEC digital I/O is provided by 
connectors J10, J11, J12, and J13. Test access to the 
CODEC analog ports is provided by inserting jumper JP4 to 
connect the VREC connector to the CODEC analog Rx 
output, and by inserting jumper JP15 to the correct Tx gain 
setting for the CODEC under test. The RSLIC should be 
removed during CODEC testing otherwise unwanted loading 
of the CODEC analog Tx input signal could result. This set-
up is summarized in Table 8.

CODEC Measurement Capability

The user should refer to the device data sheet for correct 
parameter values.

CODEC measurements include:

1. CODEC supply current (RSLIC removed).

2. A-D, D-A gain and frequency parameters.

3. A-law, mu-law companding measurements (JP8).

4. Power down measurements (JP9).

TABLE 3. EVALUATION BOARD CONNECTOR DESCRIPTIONS

CONNECTOR

DESCRIPTION

J1

RJ11 type phone connector.

J2

Ring terminal of board.

J3

Tip terminal of board.

J4

Grounding lug connected to board ground plane.

J5

1: V

CC

. Positive 5V supply to CODEC, RSLICU6, clock generator and logic devices (red wire).

2: V

BH

. High negative battery supply to the HC55185 device (orange wire).

3: V

BL

. Low negative battery supply to the HC55185 device (yellow wire).

4: +5V. Positive 5V supply to the RSLIC LED detector output indicators (green wire).

7 thru 10: GND. Twisted pair returns for external supply connections (black wires).

J6

Identical pinout as J5. Either connector provides daisy chain connection to second board for back to back evaluation.

J7

Transmit analog output from the RSLIC device, VTX. This path is AC coupled and can be used to measure G2-4W of the RSLIC. 
The A-D Tx path of the CODEC can be measured using VTX as the signal input, but the RSLIC must be removed due to the 
loading effect of the low impedance VTX output.

J8

Receive analog input to the RSLIC, VREC. This path is AC coupled and can be used to measure G4-2W of the RSLIC. Jumper 
JP4 must be removed to disconnect the low impedance CODEC output. J8 can also be used to measure the D-A Rx gain of the 
CODEC by re-inserting jumper JP4.

J9

Ringing input to HC55185 device, VRS. This path is AC coupled by C

RS

.

J10

Serial transmit data output of CODEC U6.

J11

Serial receive data input to CODEC U6.

J12

Common frame sync input for receive and transmit digital data.

J13

Common clock for CODEC data transfer and conversion.

J14

20 pin, 100 mil spacing header with all digital PCM data interfaces to CODEC U6.

J15

20 pin, 100 mil spacing header with all digital interfaces to the RSLIC.

Application Note 1168

Summary of Contents for ISL5585EVAL4

Page 1: ...M to 2W AC transmission circuits Theory of operation and the AC transmission design equations are included to enable the user to adapt the performance to meet his specific needs The operation of the r...

Page 2: ...pled by CRS Position 3 TRAP Connects the VRS connector J9 thru RC network to the device ringing input Path is AC coupled JP7 Selects the 5V or 3 3V chip set Hybrid Gain of the CODEC AC coupled by C1 J...

Page 3: ...header Refer to the specific RSLIC data sheet for detailed description of operating states Single Board Operation Description The stand alone configuration supports separate measurement of the RSLIC o...

Page 4: ...ow negative battery supply to the HC55185 device yellow wire 4 5V Positive 5V supply to the RSLIC LED detector output indicators green wire 7 thru 10 GND Twisted pair returns for external supply conne...

Page 5: ...ppearing at the tip and ring terminals Extra care is required when connecting external equipment to the tip and ring terminals during testing to prevent personnel injury and equipment damage Jumper Se...

Page 6: ...PCM4 tests can be performed on the RSLIC and the CODEC separately The RSLIC PCM4 tests use the A A tests The CODEC RX and TX gain tests use the PCM4 A D and D A tests For RSLIC gain tests the RX AC te...

Page 7: ...o the CODEC PCM output This signal path provides a measure of the trans hybrid balance for the line circuit with a 600 termination at Tip and Ring Digital Loop Back Configuration Description The digit...

Page 8: ...ed to J8 the output at JP4 should be 0 322Vrms The signal levels for digital loop back are independent of the clock selected by JP10 Dual board A A Configuration Description Two evaluation boards can...

Page 9: ...DEC master clock to 512kHz JP11 Enables the on board logic multiplexer JP12 Configures board as master SECONDARY POWER CABLE MASTER SLAVE FIGURE 4 FULL CHANNEL A A CONFIGURATION CONNECTORS AND JUMPERS...

Page 10: ...paths are connected differently The HC55185 G42 RX input is at Vrs and the gain is fixed at 0dB The ISL5585 however is required to compensate for the 3 3V CODEC attenuation i e lower 0dBm0 reference l...

Page 11: ...fixed conversion gain needed to restore the CODEC Absolute Voltage Reference Level to the 0dBm0 standard value of 0 775Vrms at 600 at the PCM bus The overall line circuit 2W to PCM gain is adjusted us...

Page 12: ...mponent Values Rp 51 Rs 66 5k Rin 37 4k ZO RS 133 3 G42 Rs Rin G24 ZO ZO 2RP ZL G44 Rs Rin ZL 2RP ZL 2RP ZO FIGURE A2 ISL5585 HYBRID BLOCK DIAGRAM TABLE A2 ISL5585 TRSANS HYBRID BALANCE EQUATIONS ISL5...

Page 13: ...99 G42 0dB G24 7 63dB G44 0 416 7 63dB ZO RS 133 3 G42 2 ZL ZL 2RP ZO G24 ZO ZO 2RP ZL G44 ZO ZL 2RP ZO FIGURE B2 HC55185 HYBRID BLOCK DIAGRAM TABLE B2 HC55185 TRANS HYBRID BALANCE EQUATIONS HC55185 W...

Page 14: ...C E0 1 2 JP4 CODEC 5v 3 3v 3 3v 5v 5v RIN 37 4K 1 CP 1 2 3 B1100CC TECCOR Q2 CR4 1N4935 CR5 1N4935 1 1 J7 VXMIT 1 1 J8 VREC PWR CONN 24V 72 to 100V CRX 0 4uF CODEC CFB 0 47uF 1 2 3 JP13 RP 0 Ohm 1 RS...

Page 15: ...Intersil or its subsidiaries For information regarding Intersil Corporation and its products see www intersil com January 24 2005 ISL5585EVAL4 Electrical Component List COMPONENT VALUE TOLERANCE RATI...

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