Intel X38ML - Server Board Motherboard Technical Manual Download | Manualshive

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Platform Management

Intel® Server Board X38ML

Revision

1.3

Intel order number E15331-006

70

used to manually force the fan domain speed to a selected value, overriding any other control or
policy.

The fan domain state is controlled by several factors. They are listed below in order of
precedence, from high to low:

Boost

-

An associated fan is in a critical state or missing. The reference document describes

which fan domains are boosted in response to a fan failure or removal in each
domain.

-

Any associated temperature sensor is in a critical state. The reference document

describes which temperature threshold violations cause fan boost for each fan
domain.

-

The chassis cover is missing.

-

If any of the above conditions apply, the fans are set to a fixed boost state speed,

specified in the Tcontrol OEM SDRs.

Sleep

-

No boost conditions, system in ACPI S1 sleep state. In this situation, fans are set to

a fixed sleep state speed, specified in the Tcontrol OEM SDRs. The BMC can
support normal fan speed control in the S1 sleep state, so the BIOS does not enable
APCI fan control.

Nominal

-

See Section 5.16.2.

5.16.1

Fan Domains

System fan speeds are controlled through pulse width modulation (PWM) signals, which are
driven separately for each domain by integrated PWM hardware. Fan speed is changed by
adjusting the duty-cycle, which is the percentage of time the signal is driven high in each pulse.

The BMC controls the average duty-cycle of each PWM signal through direct manipulation of
the integrated PWM control registers.

The same device may drive multiple PWM signals. For system-specific fan domains,
see Table 35.

Table 35. System Fan Domains

Domain Location

Fans

Output

0

System Fan 1 (refer to Figure 1 label 29.)

DIMM Fan

PWM0

1

System Fan 2 (refer to Figure 1 label 30.)

Use for other chassis

PWM1

2

System Fan 3 (refer to Figure 1 label 31.)

CPU blower

PWM2

5.16.2

Nominal Fan Speed

You can configure a fan domain’s nominal fan speed as static (fixed value) or it can be
controlled by the state of one or more associated temperature sensors.

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Summary of Contents for X38ML - Server Board Motherboard

Page 1: ...Intel Server Board X38ML Technical Product Specification Intel order number E15331 006 Revision 1 3 June 2010 Enterprise Platforms and Services Division Marketing ...

Page 2: ...evision History Date Revision Number Modifications September 2007 1 0 Initial release May 2008 1 1 iBMC fix to Integrated the BMC and fix the FAN sensors April 2009 1 2 Corrected the heading typo at the top of some even numbered page June 2010 1 3 Updated China CCC CNCA related information ...

Page 3: ...or conflicts or incompatibilities arising from future changes to them The Intel Server Board X38ML may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Intel Corporation server baseboards support peripheral components and contain a number of high density VLSI and power deliver...

Page 4: ...egrated Baseboard Management Controller 12 3 3 1 Functionality Overview 12 3 3 2 Block Diagram 14 3 4 Memory Subsystem 15 3 4 1 Memory Support 15 3 4 2 Memory Population Rules 15 3 5 I O Subsystem 16 3 5 1 PCI Express x16 Riser Slot 16 3 5 2 SATA Support 16 3 5 3 Video Support 17 3 5 4 Network Interface Controller NIC 17 3 5 5 USB Support 17 3 5 6 Super I O Chip 18 3 6 Replacing the Back Up Batter...

Page 5: ... On LAN WOL 58 5 3 Advanced Configuration and Power Interface ACPI 58 5 3 1 ACPI Power Control 58 5 3 2 ACPI State Synchronization 59 5 4 System Reset Control 59 5 4 1 Reset Signal Output 59 5 4 2 Reset Control Sources 59 5 4 3 Front Panel System Reset 59 5 4 4 Soft Reset and Hard Reset 59 5 4 5 BMC Command Used to Reset System 60 5 4 6 Watchdog Timer Expiration 60 5 5 BMC Reset Control 60 5 5 1 B...

Page 6: ...Erasure 65 5 12 Sensor Data Record SDR Repository 65 5 12 1 SDR Repository Erasure 65 5 12 2 Initialization Agent 66 5 13 Field Replaceable Unit FRU Inventory Device 66 5 13 1 BMC FRU Inventory Area Format 66 5 14 Sensor Rearm Behavior 67 5 15 Processor Sensors 68 5 15 1 Processor Status Sensors 68 5 15 2 Digital Thermal Sensor 69 5 16 Standard Fan Management 69 5 16 1 Fan Domains 70 5 16 2 Nomina...

Page 7: ...ures Implemented by BIOS 83 5 23 1 IPMI 84 5 23 2 Console Redirection 84 5 23 3 IPMI Serial Interface 85 5 23 4 Wired For Management WFM 88 5 23 5 System Management BIOS SMBIOS 88 5 23 6 Security 88 6 Error Reporting and Handling 90 6 1 Fault Resilient Booting 90 6 1 1 BSP POST Failures FRB 2 90 6 1 2 Operating System Load Failures OS Boot Timer 90 6 2 Error Handling and Logging 91 6 2 1 Error Sou...

Page 8: ...on Header 110 7 8 Jumper Blocks 111 8 Design and Environmental Specifications 112 8 1 Server Board Design Specification 112 8 2 Product Regulatory Compliance 112 8 2 1 Product Safety Compliance 112 8 2 2 Product EMC Compliance Class A Compliance 112 8 2 3 Certifications Registrations Declarations 113 8 2 4 Product Ecology Requirements 113 Product Regulatory Compliance Markings 113 8 2 5 113 8 3 El...

Page 9: ...Configuration Screen Display 37 Figure 13 Setup Utility Security Screen Display 38 Figure 14 Setup Utility Server Management Screen Display 39 Figure 15 Setup Utility Console Redirection Screen Display 41 Figure 16 Setup Utility System Information Screen Display 42 Figure 17 Setup Utility Boot Options Screen Display 43 Figure 18 Setup Utility Hard Disk Order Screen Display 44 Figure 19 Setup Utili...

Page 10: ... Configuration Screen Fields 37 Table 14 Setup Utility Security Screen Fields 38 Table 15 Setup Utility Server Management Screen Fields 39 Table 16 Setup Utility Console Redirection Configuration Fields 41 Table 17 Setup Utility System Information Fields 42 Table 18 Setup Utility Boot Options Screen Fields 43 Table 19 Setup Utility Hard Disk Order Fields 44 Table 20 Setup Utility CDROM Order Field...

Page 11: ... 97 Table 48 POST Progress Code LED Example 98 Table 49 POST Code Checkpoints 98 Table 50 POST Error Messages and Handling 101 Table 51 Power Connector Pin out J4K1 104 Table 52 PCI Express x16 Connector Pin out J7B1 104 Table 53 SMBus Connector Pin out J3C1 106 Table 54 Front Panel 16 Pin Header Pin out J5K4 106 Table 55 VGA Connector Pin out J8A1 107 Table 56 NIC1 Intel 82575EB 10 100 1000 Conne...

Page 12: ...List of Tables Intel Server Board X38ML Revision 1 3 Intel order number E15331 006 xii This page intentionally left blank ...

Page 13: ...and power delivery components that require adequate airflow to cool Intel develops and tests chassis to work with Intel server building blocks so the fully integrated system will meet the thermal requirements of all components If Intel server building blocks are not used in the system the system integrator must consult vendor datasheets and operating parameters to determine the air flow requiremen...

Page 14: ...ore Intel Xeon Processor 3075 Dual Core Intel Xeon Processor 3070 Dual Core Intel Xeon Processor 3065 Dual Core Intel Xeon Processor 3060 Dual Core Intel Xeon Processor 3050 Dual Core Intel Xeon Processor 3040 Intel Pentium Dual Core Processor E2220 Intel Pentium Dual Core Processor E2180 Intel Pentium Dual Core Processor E2160 Intel Pentium Dual Core Processor E2140 Intel Core 2 Quad Processor Q9...

Page 15: ...ntroller Memory subsystem DDR2 667 800 MHz unbuffered ECC memory or non ECC memory Two memory channels two DIMM sockets per channel 8 GB supported Video o 32 MB DDR2 667 MHz video memory o External VGA connector PCI Express connector One PCI Express x16 connector supporting PCI Express riser card HDD Interface o Four SATA II 300 Gb s ports USB o Two external USB 2 0 ports on rear I O panel o Two i...

Page 16: ...S Manufacturing o Surface mount technology double sided assembly o Eight layer PCB Form factor o 13 inch by 5 9 inch 1U thermally optimized design 2 2 Server Board Layout Ref Description Ref Description 1 J1A2 BIOS Recovery Mode jumper J1A3 CMOS Clear jumper J1A4 Integrated BMC Boot Block Write Protect jumper 17 SATA Port 3 2 Bottom USB Port 0 Middle USB Port 1 Top NIC1 RJ 45 connector 18 SATA Por...

Page 17: ... ServerEngines Integrated BMC 24 DIMM socket A2 9 POST LED 25 DIMM socket A1 10 2x5 USB header for USB 2 and 3 26 Intel X38 MCH 11 Intel 82575EB LAN controller 27 LGA775 processor socket 12 SMBus connector 28 2x9 main power connector 13 Intel 82801IR ICH9R 29 System fan 1 8 pin 14 J6B1 Password Clear jumper 30 System fan 2 8 pin 15 PCI Express x16 riser slot 31 System fan 3 8 pin 16 SATA Port 2 32...

Page 18: ...Server Board Overview Intel Server Board X38ML Revision 1 3 Intel order number E15331 006 6 Figure 2 Intel Server Board X38ML Mechanical Drawing ...

Page 19: ...e Revision 1 3 Intel order number E15331 006 7 3 Functional Architecture This chapter provides a high level description of the functionality associated with the architectural blocks that make up the server board R Figure 3 Server Board Block Diagram ...

Page 20: ...does not provide support for the following processors Intel Pentium 4 Processor Extreme Edition Intel Pentium D Processor Intel Pentium 4 Processor Intel Celeron D Processor Table 1 Processor Support Matrix Processor Family Processor Number Clock Speed Front Side Bus L2 Cache Dual Core Intel Xeon Processor 3000 sequence 3070 2 66 GHz 1066 MHz 4 MB Quad Core Intel Xeon Processor 3200 sequence X3210...

Page 21: ... x16 ports One PCI Express x16 port is connected to one PCI Express X16 connector as shown in the block diagram Compliant with the PCI Express base specification revision 2 0 3 2 2 I O Controller Hub Intel ICH9 R The Intel ICH9 R component integrates bridge functionality for PCI Express LPC USB SATA II IDE and SMBus and numerous board management functions The ICH9R is packaged in a 31 mm x 31 mm 6...

Page 22: ... transfers and channels 5 to 7 are hardwired to 16 bit count by word transfers DMA Channel 4 is used to cascade the two 8327 controllers together The DMA controller is used to support the LPC DMA The LPC DMA is handled through the LDRQ lines from peripherals and special encoding on LAD 3 0 from the host The timer counter block contains three counters that are equivalent in function to those found ...

Page 23: ...R provides a SMBus 2 0 compliant Host Controller that allows the processor to communicate with SMBus slaves This interface is compatible with most I2 C devices The ICH9R also supports slave functionality The SMBus logic exists in Device 31 Function 3 configuration space 3 2 2 11 Serial Peripheral Interface SPI The Serial Peripheral Interface SPI is a 4 pin interface that provides a potentially low...

Page 24: ...terrupts and power management events Intruder Detect input for system cases 3 3 Integrated Baseboard Management Controller A ServerEngines Baseboard Management Controller Integrated BMC is integrated onto the server board This integrates the baseboard management controller BMC and KVMS subsystem graphics controller graphics subsystem and Super I O interface Super I O subsystem The Intel Server Boa...

Page 25: ...n and redirection logic Supports both text and graphics redirection Hardware assisted video redirection using the frame processing engine Direct interface to the Integrated Graphics Controller registers and Frame buffer Hardware based encryption engine Graphics controller Integrated graphics core 2D hardware graphics acceleration DDR2 memory interface supports up to 128 Mbytes of memory Supports a...

Page 26: ...I Flash bridge which can be used to store multiple copies of the system ROM The PCI Express interface is mainly used for the graphics controller interface to the host The graphics controller is a fully compliant VGA controller with 2D hardware acceleration and full bus master support The graphics controller can support up to 1600 x1200 resolutions at high refresh rates The USB 1 1 is used for the ...

Page 27: ...is 8 GB using four DIMMs of 2 GB unbuffered 1 Gbit DDR2 memory Only DIMMs tested and qualified by Intel or a designated memory test vendor are supported A list of qualified DIMMs is at http support intel com support motherboards server X38ML Note All DIMMs are supported by design but only fully qualified DIMMs are supported on the board 3 4 2 Memory Population Rules The X38 MCH supports two DDR2 D...

Page 28: ...s the same For dual channel asymmetric mode DIMM sockets may be populated in any order 3 5 I O Subsystem 3 5 1 PCI Express x16 Riser Slot The server board provides a PCI Express x16 riser slot that is resourced with a PCI Express x16 interface from MCH and supports PCI Express x16 graphics 3 5 2 SATA Support The server board provides four SATA II ports by the integrated SATA controller of the Inte...

Page 29: ...3 5 3 Video Support The Integrated BMC integrates a fully compliant VGA graphics controller with hardware acceleration for BLIT and 2D graphics The graphics controller Is resourced with a PCI Express x1 interface from the ICH9R Supports 16 bit DDR2 memory running at a configurable frequency of 500 MHz The maximum capacity is 128 MB Supports all display resolutions up to 1600 x 1200 16bpp 75Hz 3 5 ...

Page 30: ...rts compatible with the 16C550 Up to 16 shared GPIO ports Programmable wake up event support Plug and play register set Power supply control Watchdog timer compliant with Microsoft SHDG LPC to SPI bridge for system BIOS support Real time clock module with the external RTC interface 3 5 6 1 Serial Ports The board provides two serial ports Serial A is a standard DB 9 interface located at the rear I ...

Page 31: ... of power When the battery starts to weaken it loses voltage and the server settings stored in CMOS RAM in the RTC for example the date and time may be incorrect Contact your customer service representative or dealer for a list of approved devices WARNING Danger of explosion if battery is incorrectly replaced Replace only with the same or equivalent type recommended by the equipment manufacturer D...

Page 32: ...te Använd samma batterityp eller en ekvivalent typ som rekommenderas av apparattillverkaren Kassera använt batteri enligt fabrikantens instruktion VAROITUS Paristo voi räjähtää jos se on virheellisesti asennettu Vaihda paristo ainoastaan laitevalmistajan suosittelemaan tyyppiin Hävitä käytetty paristo valmistajan ohjeiden mukaisesti ...

Page 33: ...ear HH Two digit hour using 24 hour clock M Two digit minute For example BIOS Build 3 generated on Jan 21 2006 at 11 59 AM has the following BIOS ID string displayed in the POST diagnostic screen S3200X38 86B 01 00 0003 012120061159 The BIOS version in the Setup Utility is displayed as S3200X38 86B 01 00 0003 The BIOS ID is identifies the BIOS image It is not used to designate the board ID S3200X3...

Page 34: ...eens Each page contains information or links to other pages The Advanced tab in Setup displays a list of general categories as links These links lead to pages containing a specific category s configuration The following sections describe the look and behavior for BIOS Setup 4 3 1 Operation The BIOS Setup utility is only available in English It is functional via console redirection over various ter...

Page 35: ...n Press F2 to enter setup Serious errors cause the system to enter the BIOS setup The error manager screen will display in this occurrence 4 3 1 3 Keyboard Commands The bottom right portion of the Setup screen provides a list of commands to navigate through the Setup utility These commands are displayed at all times Except for features used for informative purposes each feature on each Setup menu ...

Page 36: ...en fields For example you can use Tab to move from hours to minutes in the time item in the main menu Change Value The minus key on the keypad is used to change the value of the current item to the previous value This key scrolls through the values in the associated pick list without displaying the full list Change Value The plus key on the keypad is used to change the value of the current menu it...

Page 37: ...o serve as a reference point The Comments column provides additional information where it may be helpful This information does not display in the BIOS Setup screens Information in the screen shots that is enclosed in brackets indicates text that varies depending on the option s installed For example Current Date is replaced by the actual current date Information that is enclosed in square brackets...

Page 38: ...talled Quiet Boot Enabled Disabled POST Error Pause Enabled Disabled System Date Current Date System Time Current Time Figure 5 Setup Utility Main Screen Display Table 6 Setup Utility Main Screen Fields Setup Item Options Help Text Comments Logged in as N A N A Information only Displays password level that setup is running in Administrator or User With no passwords set Administrator is the default...

Page 39: ...ause Enabled Disabled Enabled Go to the Error Manager for critical POST errors Disabled Attempt to boot and do not go to the Error Manager for critical POST errors The POST error pause takes the system to the error manager to review the errors when Major errors occur Minor and Fatal error displays are not affected by this setting See Section 6 3 3 for more information System Date Day of week MM DD...

Page 40: ...on N A View Configure memory information and settings N A SATA Controller Configuration N A View Configure SATA Controller information and settings N A Serial Port Configuration N A View Configure serial port information and settings N A USB Configuration N A View Configure USB information and settings N A PCI Configuration N A View Configure PCI information and settings N A 4 3 2 2 1 Processor Co...

Page 41: ...led Figure 7 Setup Utility Processor Configuration Screen Display Table 8 Setup Utility Processor Configuration Screen Fields Setup Item Options Help Text Comments Processor Family N A N A Information only Identifies family or generation of the processor Core Frequency N A N A Information only Frequency at which processors currently run Maximum Frequency N A N A Information only Maximum frequency ...

Page 42: ...ocessing sets the state of logical processor cores in a package Disabled sets only logical processor core 0 as enabled in each processor package Note If disabled Hyper Threading Technology is also automatically disabled N A Intel Virtualization Technology Enabled Disabled Intel Virtualization Technology allows a platform to run multiple operating systems and applications in independent partitions ...

Page 43: ...y Table 9 Setup Utility Memory Configuration Screen Fields Setup Item Options Help Text Comments Total Memory N A N A Information only The amount of memory available in the system in the form of installed DIMMs in units of MB or GB Effective Memory N A N A Information only The amount of memory available to the operating system in MB or GB The Effective Memory is the difference between Total Physic...

Page 44: ...ed in this slot is faulty malfunctioning Memory Correction ECC Non ECC N A N A 4 3 2 2 3 SATA Controller Configuration Screen The SATA Controller Configuration screen provides fields to configure SATA hard drives It also provides information on the hard disk drives installed To access this screen from the Main screen select Advanced SATA Controller Advanced SATA Controller Configuration Onboard SA...

Page 45: ...ected The identification and configuration is left to the AHCI Option ROM Only devices supported by the AHCI Option ROM are displayed in setup SATA HDD and SATA CDROM other devices are available in the operating system after their drivers are loaded When RAID is selected no SATA drive information is displayed SATA Port 0 Not Installed Drive information N A Information only Unavailable when RAID Mo...

Page 46: ...ext Comments Serial A Enable Enabled Disabled Enable or Disable Serial port A N A Address 3F8h 2F8h 3E8h 2E8h Select Serial port A base I O address N A IRQ 3 4 Select Serial port A base interrupt request IRQ line N A Serial B Enable Enabled Disabled Enable or Disable Serial port B N A Address 3F8h 2F8h 3E8h 2E8h Select Serial port B base I O address N A IRQ 3 4 Select Serial port B base interrupt ...

Page 47: ...USB Controller Enabled Disabled Legacy USB Support Enabled Disabled Auto USB Mass Storage Device Configuration Device Reset timeout 10 sec 20 sec 30 sec 40 sec Storage Emulation Mass storage devices one line device Auto Floppy Forced FDD Hard Disk CD ROM USB 2 0 controller Enabled Disabled Figure 11 Setup Utility USB Controller Configuration Screen Display ...

Page 48: ...40 sec USB Mass storage device Start Unit command timeout N A Storage Emulation Header for next line One line for each mass storage device in system Auto Floppy Forced FDD Hard Disk CD ROM Auto USB devices less than 530 MB will be emulated as floppy Forced FDD HDD formatted drive will be emulated as FDD e g ZIP drive This setup screen can show a maximum of eight devices on this screen If more than...

Page 49: ... system video The onboard video controller will be the primary video device N A Onboard NIC ROM Enabled Disabled Load the embedded option ROM for the onboard network controllers Warning If Disabled is selected NIC1 and NIC2 cannot be used to boot or wake the system N A NIC 1 MAC Address No entry allowed N A Information only 12 hex digits of the MAC address NIC 2 MAC Address No entry allowed N A In...

Page 50: ...rol change access in BIOS Setup Utility Only alphanumeric characters can be used Maximum length is 7 characters It is not case sensitive Note Administrator password must be set in order to use the user account This option is only to control access to setup Administrator has full access to all setup items Clearing the Admin password also clears the user password Set User Password 123abcd User passw...

Page 51: ... Timer Enabled Disabled O S Boot Watchdog Timer Policy Power off Reset O S Boot Watchdog Timer Timeout 5 minutes 10 minutes 15 minutes 20 minutes Console Redirection System Information Figure 14 Setup Utility Server Management Screen Display Table 15 Setup Utility Server Management Screen Fields Setup Item Options Help Text Comments Assert NMI on SERR Enabled Disabled On SERR generate an NMI and l...

Page 52: ...anagement Software N A O S Boot Watchdog Timer Policy Power Off Reset If the OS watchdog timer is enabled this is the system action taken if the watchdog timer expires Reset System performs a reset Power Off System powers off N A O S Boot Watchdog Timer Timeout 5 minutes 10 minutes 15 minutes 20 minutes If the OS watchdog timer is enabled this is the timeout value BIOS will use to configure the wa...

Page 53: ...onfigure serial port A for console redirection Serial Port B Configure serial port B for console redirection Enabling this option will disable the Quiet Boot logo screen during POST N A Flow Control None RTS CTS Flow control is the handshake protocol Setting must match the remote terminal application None Configure for no flow control RTS CTS Configure for hardware flow control N A Baud Rate 9600 ...

Page 54: ...Chassis Part Number Chassis Serial Number BMC Firmware Revision HSC Firmware Revision SDR Revision UUID Figure 16 Setup Utility System Information Screen Display Table 17 Setup Utility System Information Fields Setup Item Options Help Text Comments Board Part Number N A N A Information Only Board Serial Number N A N A Information Only System Part Number N A N A Information Only System Serial Numbe...

Page 55: ...igure 17 Setup Utility Boot Options Screen Display Table 18 Setup Utility Boot Options Screen Fields Setup Item Options Help Text Comments Boot Timeout 0 65535 The number of seconds BIOS will pause at the end of POST to allow the user to press the F2 key to enter the BIOS Setup Utility Valid values are 0 65535 Zero is the default A value of 65535 will cause the system to go to the Boot Manager men...

Page 56: ...Order N A Set the Bootstrap Entry Vector BEV device boot order by selecting the boot option for this position BEV devices require their own proprietary method to load an OS using a bootable option ROM BEV devices are typically found on remote program load devices Displays when more than one of these devices is available in the system 4 3 2 5 1 Hard Disk Order Screen The Hard Disk Order screen prov...

Page 57: ...evices Set CD ROM boot order by selecting the boot option for this position N A 4 3 2 5 3 Floppy Order Screen The Floppy Order screen provides a way to control the floppy drives To access this screen from the Main screen select Boot Options Floppy Order Boot Options Floppy Disk 1 Available Floppy Disk Floppy Disk 2 Available Floppy Disk Figure 20 Setup Utility Floppy Order Screen Display Table 21 ...

Page 58: ... Available network devices Set network device boot order by selecting the boot option for this position Add in or onboard network devices with a PXE option ROM are two examples of network boot devices N A Network Device 2 Available network devices Set network device boot order by selecting the boot option for this position Add in or onboard network devices with a PXE option ROM are two examples of...

Page 59: ...V Device 2 Available BEV devices Set the Bootstrap Entry Vector BEV device boot order by selecting the boot option for this position BEV devices require their own proprietary method to load an OS using a bootable option ROM BEV devices are typically found on remote program load devices N A 4 3 2 6 Boot Manager The Boot Manager screen displays a list of devices available to boot from and allows the...

Page 60: ... POST Error Manager Exit ERROR CODE SEVERITY INSTANCE Figure 24 Setup Utility Error Manager Screen Display Table 25 Setup Utility Error Manager Screen Fields Setup Item Options Help Text Comments Displays System Errors N A N A Information only Displays errors that occurred during this POST 4 3 2 8 Exit Screen The Exit screen allows the user to choose to save or discard the configuration changes ma...

Page 61: ... modified Save Changes Save changes without exiting BIOS Setup Utility Note Saved changes may require a system reboot before taking effect User is prompted for confirmation only if any of the setup fields were modified Discard Changes Discard changes made since the last save changes operation was performed User is prompted for confirmation only if any of the setup fields were modified Load Default...

Page 62: ...hed then the code within the boot block remains intact and could be used to recover the system through peripherals such as a floppy CD ROM or USB drive Now the BIOS is more complicated and a single boot block faces space constraints This platform introduces multiple boot blocks as a way to remove the space constraints while maintaining the boot blocks fault tolerant capability For this platform th...

Page 63: ... the recovery media SATA CD or USB disk This process takes place before any video or console is available 4 The BIOS POST screen appears and displays the progress The user selects the option to boot the EFI SHELL which is embedded in the BIOS The system boots the EFI SHELL 5 The user runs Update NSH This is an auto executed script file that uses the new capture file CAP The system loads and execut...

Page 64: ...r number E15331 006 52 The logo file must follow the standard framework format for graphical images The size must not exceed 800 x 512 pixels The number of colors cannot exceed 256 although the actual number of colors may be limited due to image size constraints ...

Page 65: ...ment Protocol SNMP alerts via LAN interfaces Platform event filtering PEF device Event receiver device The BMC receives and processes events from other platform subsystems Field replaceable unit FRU inventory device functionality The BMC supports access to system FRU devices using IPMI FRU commands System event log SEL device functionality The BMC supports and provides access to a SEL Sensor devic...

Page 66: ...ol ARP The BMC sends and responds to ARP supported on embedded NICs Dynamic Host Configuration Protocol DHCP The BMC performs DHCP supported on embedded NICs Chassis intrusion fan interactions Fans switch to high speed when the chassis intrusion signal is asserted Platform environment control interface PECI thermal management support Simple Network Management Protocol SNMP v1 v2 and v3 5 2 Power S...

Page 67: ...erval can be set longer to add flexibility in manufacturing test environments The POWER_GOOD signal must remain stable and not glitch when asserted The BMC uses the state of the PS_PWRGD signal to monitor whether the power supply is on and operational and to confirm whether the system power state matches the intended system on off power state that was commanded with the PS_ON signal 5 2 2 Power Go...

Page 68: ...r button being pressed for 8 seconds or until PS_PWRGD is deasserted If PS_PWRGD is not deasserted within 8 seconds then a fault is generated See Section 5 17 3 Before initiating the system power down the BMC stops scanning any sensors that should not be scanned in the powered down state 5 2 5 Power Control Sources The following sources can initiate power up and or power down activity Table 27 Pow...

Page 69: ... will power on When AC power is applied the BMC disables the SIO power button output After the BMC has completed a specific phase of its initialization it re enables this output This prevents potential race conditions between the BMC and the BIOS The BMC monitors the Sleep S4 S5 signals to detect if the chipset is attempting to power on the system If so the BMC completes necessary transitional ope...

Page 70: ...ing table Table 28 ACPI Power States State Supported Description S0 Yes Working The front panel power LED is on not controlled by the BMC The fans spin at the normal speed as determined by sensor inputs Front panel buttons work normally S1 Yes Sleeping Hardware context maintained equates to processor and chipset clocks stopped The front panel power LED blinks at a rate of 1 Hz with a 50 duty cycle...

Page 71: ... System Reset Main system power comes up Yes Reset button or in target probe ITP reset Yes Soft reset warm boot DOS Ctrl Alt Del Yes Hard reset Yes Command to reset the system Yes Watchdog timer configured for reset Yes PEF action Optional 5 4 3 Front Panel System Reset The reset button is a momentary contact button on the front panel The signal is routed through the front panel connector to the B...

Page 72: ...hronizes to the state of the processor and power control signals it finds when it initializes 5 6 System Initialization The following items are initialized by both the BIOS and the BMC during system initialization 5 6 1 Processor TControl Setting Processors used with this chipset implement a feature called Tcontrol which provides a processor specific value that can be used to adjust the fan contro...

Page 73: ...termines during POST if a BMC watchdog timer timeout occurred on the previous boot attempt If it finds a watchdog timeout did occur it determines whether that timeout was an FRB2 timeout a system management software SMS timeout or an intentional timed hard reset The BMC provides the IPMI Get Watchdog Timer command to facilitate determining the cause of watchdog time out The BMC maintains the timeo...

Page 74: ... a degraded operation Amber fault shows the platform hardware state and overrides the green status The system status LED is controlled by the BMC Early in the startup boot process the BIOS checks the chipset for any memory errors The BMC detected states are included in the LED states For fault states monitored by BMC sensors the contribution to the LED state follows the associated sensor state wit...

Page 75: ...e status of the signal available via the Get Chassis Status command and the Physical Security sensor state A chassis intrusion state change causes the BMC to generate a Physical Security sensor event message with a General Chassis Intrusion offset 00h The BMC boosts all fans when the chassis intrusion signal is active Fans return to their previous level when the chassis intrusion signal is no long...

Page 76: ... the validity of its internal timestamp so it resets its clock counter to zero The BMC attempts to retrieve the current time from an internal battery backed RTC element If the RTC time is in the pre init range of 0 to 0x20000000 then the BMC ignores it and continues counting from zero and any SEL events have pre init timestamps relative to the approximate time of the BMC initialization Whenever th...

Page 77: ...ey are read from the event message queue This means the queue can contain duplicate messages 5 11 2 SEL Entry Deletion The BMC does not support individual SEL entry deletion The SEL may only be cleared as a whole 5 11 3 SEL Erasure SEL erasure is a background process After initiating erasure with the Clear SEL command additional Clear SEL commands must be executed to get the erasure status and det...

Page 78: ...g logged For details on the initialization agent refer to the IPMI 2 0 specification 5 13 Field Replaceable Unit FRU Inventory Device The BMC implements the interface for logical FRU inventory devices as specified in the Intelligent Platform Management Interface Specification Version 2 0 This functionality provides commands used for accessing and managing the FRU inventory information These comman...

Page 79: ...tion event 4 The sensor is put into the init in progress state until the sensor is polled again or is updated 5 The sensor is polled and the init in progress state is cleared If the condition that caused the assertion is present at the time the re arm occurs then the sequence is as follows 1 The failure condition occurs and the BMC logs an assertion event 2 The sensor is re armed 3 The BMC clears ...

Page 80: ... front panel LEDs for processor fault conditions shown in the table below For more information refer to Section 5 7 2 Table 34 Processor Status Sensor Implementation Offset Processor Status Detected By 0 Internal error IERR BMC 1 Thermal trip BMC 2 FRB1 BIST failure Not Supported 3 FRB2 Hang in POST failure BIOS 1 4 FRB3 Processor startup initialization failure CPU fails to start Not Supported 5 C...

Page 81: ...bus interface that provides a communication channel between Intel processors and chipset components to the BMC s integrated PECI subsystem The PECI bus communicates environment information such as temperature between the managed components referred to as the PECI client devices and the management controller referred to as the PECI system host The PECI standard supersedes older methods such as the ...

Page 82: ...e speed specified in the Tcontrol OEM SDRs The BMC can support normal fan speed control in the S1 sleep state so the BIOS does not enable APCI fan control Nominal See Section 5 16 2 5 16 1 Fan Domains System fan speeds are controlled through pulse width modulation PWM signals which are driven separately for each domain by integrated PWM hardware Fan speed is changed by adjusting the duty cycle whi...

Page 83: ...an be specified to minimize fan speed oscillation and to smooth fan speed transitions If a legacy Tcontrol SDR format does not allow specifying hysteresis the BMC assumes a hysteresis value of zero 5 16 3 Thermal and Acoustic Management This feature refers to enhanced fan management to keep the system optimally cooled while reducing the amount of noise generated by the system fans Aggressive acous...

Page 84: ...nal code corrupted Yes 57h 02h BMC boot firmware update code corrupted Yes 57h 04h BMC FRU internal use area corrupted Yes 57h 08h SDR repository empty Yes 57h 10h IPMB Signal Error No 57h 20h BMC FRU device inaccessible Yes 57h 40h BMC SDR repository inaccessible Yes 57h 80h BMC SEL device inaccessible Yes 5 19 Messaging Interfaces This section describes the supported BMC communication interfaces...

Page 85: ... by remote console software Requests may be directed to controllers on the IPMB but requests originating on the IPMB cannot be directed to the LAN interface 5 19 5 Request Response Protocol The protocols are request response protocols A request message is issued to an intelligent device that responds with a response message For example both request messages and response messages in the IPMB are tr...

Page 86: ...interface definition the OEM1 and OEM2 bits in the SMS and SMM interfaces are defined to provide BMC status information 5 19 6 4 Server Management Software SMS Interface The SMS interface is the BMC host interface The BMC implements the SMS KCS interface as described in the IPMI 2 0 specification The BMC implements the optional Get Status Abort transaction on this interface Only logical unit numbe...

Page 87: ...ations see The I2 C Bus and How to Use It The IPMB implementation in the BMC is compliant with the IPMB v1 0 revision 1 0 The BMC IPMB slave address is 20h The BMC sends and receives IPMB messages over the IPMB interface Non IPMB messages received by the IPMB interface are discarded Messages sent by the BMC are either originated by the BMC for example when an agent operation is initialized or on b...

Page 88: ...t should be negotiated when the IOL session is established 5 20 Event Filtering and Alerting The BMC supports the following IPMI 2 0 alerting features Platform event filtering PEF Dial paging Alert over LAN 5 20 1 Platform Event Filtering PEF The BMC monitors platform health and logs failure events into the SEL PEF provides a flexible general mechanism that enables the BMC to perform actions trigg...

Page 89: ...d reserved for future use 5 20 4 Alert Policies Associated with each PEF entry is an alert policy that determines which IPMI channel the alert is sent to There is a maximum of 16 alert policy entries There are no pre configured entries in the alert policy table because the destination types and alerts may vary by user Each entry in the alert policy table contains 4 bytes for a maximum table size o...

Page 90: ... IPMI specification depending on whether the sensor event reading type is generic or a sensor specific response Assertion Deassertion Assertion and Deassertion indicators reveal what type of events this sensor generates As Assertions De Deassertion Readable Value Offsets Readable Value indicates the type of value returned for threshold and other non discrete type sensors Readable Offsets indicates...

Page 91: ...ain system power is off but AC power is present Table 40 Intel Server Board X38ML Integrated BMC Sensors Sensor Names Sensor Sensor Type Event Reading Type Event Offset Triggers Contrib To System Status Assert De assert Readable Value Offsets Event Data Rearm Stand by Power Unit Power down A C lost OK X 01h Power Unit 09h Sensor Specific 6Fh Soft power control failure Fatal As and De N A Trig Offs...

Page 92: ... and De Analog R T A N A 3 3V 06h Voltage 02h Threshold 01h u l nr c nc nc Degra ded c Non fatal As and De Analog R T A N A 3 3V Standby 07h Voltage 02h Threshold 01h u l nr c nc nc Degra ded c Non fatal As and De Analog R T A N A 5V 08h Voltage 02h Threshold 01h u l nr c nc nc Degra ded c Non fatal As and De Analog R T A N A Fan 1 Tachometer 09h Fan 04h Threshold 01h l c nc nc Degra ded c Non fat...

Page 93: ...04h Threshold 01h l c nc nc Degra ded c Non fatal2 As and De Analog R T M N A Fan 5 Tachometer 0Dh Fan 04h Threshold 01h l c nc nc Degra ded c Non fatal2 As and De Analog R T M N A Fan 6 Tachometer 0Eh Fan 04h Threshold 01h l c nc nc Degra ded c Non fatal2 As and De Analog R T M N A VccP Processor 0Fh Voltage 02h Threshold 01h u l nr c nc nc Degra ded c Non fatal As and De Analog R T A N A Process...

Page 94: ...e 1 For systems with redundant cooling capability the contribution to system status is determined by the fan redundancy sensor 2 Sensor name strings in the SDR may vary from the names in this table 3 This sensor is only present on systems with redundant components for example fan or power supply ...

Page 95: ... with the BMC s SOL feature to provide console redirection via SOL See Section 5 19 8 1 BIOS SEL logging The BIOS logs SEL events using the Platform Event Message command Disable PEF on entry to setup Per the recommendation in the PEF Startup Delay section of the IPMI 2 0 specification the BIOS disables the PEF when the BIOS Setup Utility is run and restores it when the BIOS Setup utility is exite...

Page 96: ...ugh a serial link serial port When console redirection is enabled the local host server keyboard input and video output are passed both to the local keyboard and video connections and to the remote console through the serial link Keyboard inputs from both sources are considered valid and video is displayed to both outputs You can also control the system from a remote console so a host keyboard or ...

Page 97: ...e management controller via the Intelligent Platform Management Bus IPMB 5 23 3 IPMI Serial Interface The system provides a communication serial port with the BMC A multiplexer controlled by the BMC determines if the COM1 external connector is electrically connected to the BMC or to the standard serial port of the Super I O See Section 14 titled IPMI Serial Modem Interface in the Intelligent Platf...

Page 98: ...s an extra control escape sequence to force the COM port to the BMC After this command is sent the COM1 port attaches to the BMC Channel Access serial port and Super I O COM1 data is ignored This feature allows a remote user to monitor the status of POST using the standard BIOS console redirection features and then take control of the system reset or power using the Channel Mode features If a fail...

Page 99: ... on Serial port A Example 2 Console Redirection is enabled on Serial A with Baud 115200 Flow Control CTS RTS Terminal Type VT100 SOL Not Active The BIOS sends data on Serial A port with 115200 Baud with flow control CTS RTS enabled and it emulates terminal Type VT100 In summary the BIOS uses the BIOS Setup utility to perform Console Redirection on Serial A SOL Found Active The BIOS prioritizes SOL...

Page 100: ...eveloper intel com technology framework The BIOS supports legacy PXE option ROMs in legacy mode and includes the necessary PXE ROMs in the BIOS image for the onboard controllers The legacy PXE ROM is required to boot a non EFI operating system over the network 5 23 5 System Management BIOS SMBIOS The BIOS provides support for the System Management BIOS Reference Specification Version 2 5 to create...

Page 101: ...d to exit the halt state This feature makes it difficult to break the password by guessing at it 5 23 6 1 Password Clear Jumper If the user and or administrator password is lost or forgotten you can clear both passwords by moving the password clear jumper into the clear position The BIOS determines if the password clear jumper is in the clear position during BIOS POST and clears any existing passw...

Page 102: ...during POST before the BIOS disables the FRB 2 timer the BMC generates an asynchronous system reset ASR The BMC retains status bits that the BIOS can read later in POST so the appropriate event can be entered in the system event log and the appropriate error message is displayed When an FRB 2 timeout occurs the BIOS will not send a Set Fault Indication In the case of an FRB 2 failure the system wi...

Page 103: ...rors including errors that can generate an NMI The SMI handler sends a command to the BMC to log the event and provides the data to be logged For example the BIOS programs the hardware to generate an SMI on a single bit memory error and logs the location of the failed DIMM in the system event log System events handled by the BIOS generate an SMI After the BIOS finishes logging the error it asserts...

Page 104: ...annot determine the location of the bad DIMM The uncorrectable errors may have corrupted the contents of SMRAM The SMI handler will log the failing DIMM number to the BMC if the SMRAM contents are still valid The ability to isolate the failure down to a single DIMM may not be available with certain errors and or during early POST The format of the data bytes is described in Section 6 2 3 1 6 2 2 5...

Page 105: ... Version 2 0 The system BIOS sensors are logical entities that generate events The BIOS ensures each combination of sensor type such as memory and event type sensor specific has a unique sensor number 6 2 3 1 Memory Error Events Table 42 Memory Error Events Field IPMI Definition BIOS Implementation Generator ID 7 1 System software ID or IPMB slave address 1 ID is system software ID 0 ID is IPMB sl...

Page 106: ...rrectable error no information about the error is available 0x20 0xFF 0xFF Uncorrectable memory error failed FBDIMM is the fifth FBDIMM on the second memory card 0x21 0xFF 0x44 Bits 7 6 01 Bits 5 0 04 6 2 3 3 PCI Error Events Table 44 PCI Error Events Field IPMI Definition BIOS Implementation Generator ID 7 1 System software ID or IPMB slave address 1 ID is system software ID 0 ID is IPMB slave ad...

Page 107: ... unspecified Event Data 3 7 0 OEM code 3 or unspecified For format rev 0 if this byte is specified it contains the PCI device function address in the standard format 7 3 Device number of the failing PCI device 2 0 PCI function number It will always contain a zero if the device is not a multifunction device If the source of the PCI error cannot be determined this byte contains 0xff and the event da...

Page 108: ... unspecified Data 2 and Data 3 each contain part of the Watchdog timer failed on last boot error code 8190 Data 2 090h Event Data 3 7 0 OEM code 3 or unspecified Data 2 and Data 3 each contain part of the Watchdog timer failed on last boot error code 8190 Data 3 081h 6 2 4 Timestamp Clock Event The BMC maintains a 4 byte internal timestamp clock used by the SEL and SDR subsystems This clock is inc...

Page 109: ...ostic LEDs During the system boot process the BIOS executes several platform configuration processes each of which is assigned a specific hex POST code number As each configuration routine is started the BIOS displays the POST code on the POST code diagnostic LEDs found on the back edge of the server board To assist in troubleshooting a system hang during the POST process you can use the diagnosti...

Page 110: ...0x11h OFF OFF OFF A Host processor cache initialization including AP 0x12h OFF OFF G R Starting application processor initialization 0x13h OFF OFF G A SMM initialization Chipset 0x21h OFF OFF R G Initializing a chipset component Memory 0x22h OFF OFF A OFF Reading configuration data from memory SPD on FBDIMM 0x23h OFF OFF A G Detecting presence of memory 0x24h OFF G R OFF Programming timing paramet...

Page 111: ...er 0x7Ah G R A R Enabling the console controller Keyboard PS 2 or USB 0x90h R OFF OFF R Resetting the keyboard 0x91h R OFF OFF A Disabling the keyboard 0x92h R OFF G R Detecting the presence of the keyboard 0x93h R OFF G A Enabling the keyboard 0x94h R G OFF R Clearing keyboard input buffer 0x95h R G OFF A Instructing keyboard controller to run Self Test PS 2 only Mouse PS 2 or USB 0x98h A OFF OFF...

Page 112: ...stalled correctly 0xE1h R R R G Reserved for initialization module use PEIM 0xE3h R R A G Reserved for initialization module use PEIM Driver eXecution Environment DXE Core 0xE4h R A R OFF Entered EFI driver execution phase DXE 0xE5h R A R G Started dispatching drivers 0xE6h R A A OFF Started connecting drivers DXE Drivers 0xE7h R A A G Waiting for user input 0xE8h A R R OFF Checking password 0xE9h...

Page 113: ...tate The user may want to replace the erroneous unit The setup POST error Pause setting does not have any effect with this error Major The message displays in the Error Manager screen and an error is logged to the SEL The setup POST error Pause setting determines whether the system pauses to the Error Manager for this type of error where the user can take immediate corrective action or choose to c...

Page 114: ...countered a Serial Presence Detection SPD fail error Major 8580 DIMM_A1 Correctable ECC error encountered Minor Major after 10 8581 DIMM_A2 Correctable ECC error encountered Minor Major after 10 8584 DIMM_B1 Correctable ECC error encountered Minor Major after 10 8585 DIMM_B2 Correctable ECC error encountered Minor Major after 10 85A0 DIMM_A1 Uncorrectable ECC error encountered Major 85A1 DIMM_A2 U...

Page 115: ...al software state error Fatal 96A7 DXE boot services driver component encountered an illegal software state error Fatal 96AB DXE boot services driver component encountered invalid configuration Minor 96E7 SMM driver component encountered an illegal software state error Fatal 0xA027 Processor component encountered a low voltage error Minor 0xA028 Processor component encountered a high voltage error...

Page 116: ... 6 GND Black 15 PWROK Gray 7 GND Black 16 GND Black 8 P12V_VRD Yellow 17 GND Black 9 P12V_VRD Yellow 18 12V Yellow Blue Stripe 7 2 PCI Express x16 Connector One PCI Express x16 connector is provided to support PCI Express riser cards The following table defines the pin out of the PCI Express x16 connector Table 52 PCI Express x16 Connector Pin out J7B1 Pin Side B PCI Spec Signal Pin Side A PCI Spe...

Page 117: ...28 GND 29 GND 29 PERP3 30 RSVD 30 PERN3 31 PRSNT2_N 31 GND 32 GND 32 RSVD 33 PETP4 33 RSVD 34 PETN4 34 GND 35 GND 35 PERP4 36 GND 36 PERN4 37 PETP5 37 GND 38 PETN5 38 GND 39 GND 39 PERP5 40 GND 40 PERN5 41 PETP6 41 GND 42 PETN6 42 GND 43 GND 43 PERP6 44 GND 44 PERN6 45 PETP7 45 GND 46 PETN7 46 GND 47 GND 47 PERP7 48 PRSNT2_N 48 PERN7 49 GND 49 GND 50 PETP8 50 RSVD 51 PETN8 51 GND 52 GND 52 PERP8 5...

Page 118: ...82 RSVD 82 GND 7 3 SMBus Connector The following table defines the pin out of the SMBus connector on the server board Table 53 SMBus Connector Pin out J3C1 Pin Signal Name Description 1 SMB_DATA_MAIN Data Line 2 GND GROUND 3 SMB_CLK_MAIN Clock Line 7 4 Front Panel Connector A 16 pin customized header is provided to support a system front panel The header contains a reset button power control butto...

Page 119: ...e 55 VGA Connector Pin out J8A1 Signal Name Pin Signal Name Pin VGA_RED 1 5V 9 VGA_GREEN 2 GND 10 VGA_BLUE 3 RESERVED 11 RESERVED 4 DDCDAT 12 GND 5 HSYNC 13 GND 6 VSYNC 14 GND 7 DDCCLK 15 GND 8 7 5 2 NIC Connectors The server board supports two NIC RJ 45 connectors The following tables detail the pin out of the connectors Table 56 NIC1 Intel 82575EB 10 100 1000 Connector Pin out JA2A1 Signal Name ...

Page 120: ...he pin out for these four SATA connectors is defined in the following table Table 58 SATA Connector Pin out J1C1 J1C2 J2C2 J2C1 Pin Signal Name 1 GND 2 TXP 3 TXN 4 GND 5 RXN 6 RXP 7 GND 7 5 4 Serial Port Connectors One fully functional serial port and one Tx Rx only serial port is provided on the server board A standard external DB 9 serial connector is located on the back edge of the server board...

Page 121: ...tacked with an RJ 45 connector connected to NIC1 LAN signals Table 61 USB Connectors Pin out JA2A1 Pin Signal Name 1 USB PWR 2 USBP_1N 3 USBP_1P 4 GND 5 USB PWR 6 USBP_0N 7 USBP_0P 8 GND A header on the server board provides an option to support two additional USB connectors The pin out of the header is detailed in the following table Table 62 Optional USB Connection Header Pin out J1B3 Signal Nam...

Page 122: ...round 2 12V Power Fan Power 12VDC 3 TACH1 Sense FAN_TACH signal to monitor the fan speed 4 PWM1 Control Pulse Width Modulation Fan speed Control signal 1 GND Power GROUND is the power supply ground 2 12V Power Fan Power 12VDC 3 TACH2 Sense FAN_TACH signal to monitor the fan speed 4 PWM2 Control Pulse Width Modulation Fan speed Control signal 7 7 Chassis Intrusion Header A 1x2 pin header J1B2 is us...

Page 123: ... 3 CMOS Clear J1A2 BIOS Recovery Mode Force the system to boot into BIOS Recovery mode Pins 1 2 Normal Boot Default Pins 2 3 Recovery Mode J6B1 Password Clear Clear Administrator and User passwords as set in BIOS Setup Pins 1 2 Normal Boot Default Pins 2 3 Password Clear J3A1 Integrated BMC Force Update Mode Force Integrated BMC to boot into firmware update mode Pins 1 2 Normal Boot Default Pins 2...

Page 124: ...cation This product was evaluated as Information Technology Equipment ITE which may be installed in offices schools computer rooms and similar commercial type locations The suitability of this product for other product categories and environments such as medical industrial telecommunications NEBS residential alarm systems test equipment and so on other than an ITE application may require further e...

Page 125: ... required as a screening audit to verify suppliers declarations The server board complies with the following ecology regulatory requirements All materials parts and subassemblies must not contain restricted materials as defined in Intel s Environmental Product Content Specification of Suppliers and Outsourced Manufacturers http supplier intel com ehs environmental htm Europe European Directive 200...

Page 126: ...Ctick Marking Australia New Zealand RRL MIC Mark Korea 인증번호 CPU X38ML A Country of Origin Marking Marked on packaging label Exporting Requirements Made in xxxxx PB Free Marking Environmental Requirements China RoHS Marking China China Recycling Package Marking Marked on packaging label China Other Recycling Package Marking Marked on packaging label Environmental Requirements ...

Page 127: ...termined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures Reorient or relocate the receiving antenna Increase the separation between the equipment and the receiver Connect the equipment to an outlet on a circuit other than the one to which the receiver is connected Consult the dealer or an experienced radio TV te...

Page 128: ...This is a Class B product based on the standard of the Voluntary Control Council for Interference VCCI from Information Technology Equipment If this is used near a radio or television receiver in a domestic environment it may cause radio interference Install and use the equipment according to the instruction manual 8 3 5 Taiwan Declaration of Conformity BSMI The BSMI Certification Marking and EMC ...

Page 129: ... Access DMTF Distributed Management Task Force ECC Error Correcting Code EMC Electromagnetic Compatibility EPS External Product Specification ESCD Extended System Configuration Data FDC Floppy Disk Controller FIFO First In First Out FRU Field replaceable unit GB 1024 MB GPIO General purpose I O GUID Globally Unique ID Hz Hertz 1 cycle second HDG Hardware Design Guide I2C Inter integrated circuit b...

Page 130: ... RI Ring Indicate RISC Reduced instruction set computing RMCP Remote Management Control Protocol ROM Read Only Memory RTC Real Time Clock SBE Single Bit Error SCI System Configuration Interrupt SDR Sensor Data Record SDRAM Synchronous Dynamic RAM SEL System event log SERIRQ Serialized Interrupt Requests SERR System Error SM Server Management SMI Server management interrupt SMI is the highest prior...

Page 131: ...Intel Server Board X38ML Glossary Revision 1 3 Intel order number E15331 006 119 Term Definition Word 16 bit quantity ZCR Zero Channel RAID ...

Page 132: ...ration Microsoft Corporation Toshiba Corporation Intelligent Platform Management Bus Communications Protocol Specification Version 1 0 1998 Intel Corporation Hewlett Packard Company NEC Corporation Dell Computer Corporation Intelligent Platform Management Interface Specification Version 2 0 Intel Corporation Hewlett Packard Company NEC Corporation Dell Computer Corporation Platform Management FRU ...

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