Intel® Server Board X38ML
Platform Management
Revision 1.3
Intel order number E15331-006
55
Figure 26. BMC Power/Reset Signals
5.2.1
Power Supply Interface Signals
The BMC controls the
POWER_ON
signal. It connects to the chassis power subsystem and is
used to request power state changes (asserted = request power on). The
PS_PWRGD
signal
from the chassis power subsystem indicates the current power state (asserted = power is on).
Figure 26 shows the power supply control signals and their sources. To turn the system on, the
BMC asserts the
PS_ON
signal and waits for the
PS_PWRGD
signal to assert in response,
indicating DC power is on.
The
PS_PWRGD
signal is normally asserted within 1.5 seconds, but the timeout interval can be
set longer to add flexibility in manufacturing test environments. The
POWER_GOOD
signal
must remain stable and not glitch when asserted. The BMC uses the state of the
PS_PWRGD
signal to monitor whether the power supply is on and operational, and to confirm whether the
system power state matches the intended system on/off power state that was commanded with
the
PS_ON
signal.
5.2.2
Power-Good Dropout
De-assertion of the
PS_PWRGD
signal generates an interrupt that the BMC uses to detect
either power subsystem failure or loss of AC power. A power-good dropout is defined as the
PS_PWRGD
signal de-asserting when the system should be in the DC power-on state as
determined by the state of the
PS_ON
signal. If the BMC detects a power-good dropout, the
following occurs:
1. Hardware powers down the system.
2. The BMC asserts the
Power Unit Failure
offset of the
Power Unit
sensor and logs a SEL
event.
