Intel SPSH4 - Server Platform - 0 MB RAM, Technical Product Specification

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SPSH4 Server SystemTechnical Product Specification
Revision 1.11
Intel reference number 10736
13
Table 4 SSH4 Baseboard Components
Key Component Key Component
A PCI bus 64 bit, 100 MHz, Hot Plug T Chassis Intrusion Detect connector (P36)
B PCI bus 64 bit, 100 MHz, Non-Hot Plug U 14-pin Power Control connector (P35)
C PCI bus 32 bit, 33 MHz, Non-Hot Plug V 24-pin Power connector (P32)
D ICMB connector (P24) W 20-pin Power connector (P28)
E HPIB connector (P23) X Serial port B connector (P17)
F Back Panel I/O connectors) Y USB #3 Header (P18)
G Intel 82550 Ethernet controller Z Front Panel Header (P19)
H ATI* Rage* XL 2D/3D graphics accelerator AA IDE Connector (P13)
J Intel 82544 Ethernet controller BB SCSI LVD connectors (P4 and P7)
K Video RAM (VRAM) (4 MB total) CC IPMB connector (P12)
L Processor board connectors (P21 and P22) DD AIC7899 or AIC 7902 SCSI controller
M ServerWorks South Bridge Controller (CSB5) EE Fan connector (P11)
N BMC (Sahalee) component FF ServerWorks PCI-X Bus Bridge Controller (CIOB30)
P BIOS Flash component GG ServerWorks PCI-X Bus Bridge Controller (CIOB30)
Q PC87417 Super I/O controller HH RAID LED connectors (P1 and P2)
R BMC Flash component JJ HSBP connector (P16)
S Battery KK HSBP connector (P15)
The SSH4 memory subsystem consists of a single memory expansion board. This board
supports up to 12 DDR registered ECC SDRAM memory modules. The SSH4 baseboard
implementation in SPSH4 server supports both stacked and unstacked memory modules for up
to 24 GB of system memory.
The SSH4 boardset provides the following features:
•
Three interleaved memory banks.
•
Four 184 pin DIMMS per bank.
•
Banks must be populated in order.
•
Single bit error correction – If a single-bit error is detected, the ECC logic generates a new
Qword with a pattern that corresponds to the originally received 8-bit ECC parity code and
returned to the requestor (the processor or the PCI master)
•
Multi Bit error detection – Additional errors within the same Qword constitute a multibit error
which may be unrecoverable. In the case of a multi-bit error, a non-maskable interrupt (NMI)
is issued that instructs the system to shut down to avoid data corruption. ( multibit errors are
very rare ).
•
Memory Scrubbing – Error correction is performed on data being read from memory. The
correction is the passed to the requestor and at the same time is “scrubbed” or corrected in