SPSH4 Server SystemTechnical Product Specification
Revision 1.11
Intel reference number 10736
63
6.5.2 I/O
Ports
80C51 architecture provides four memory-mapped I/O ports:
•
Port #0 (P0)
•
Port #1 (P1)
•
Port #2 (P2)
•
Port #3 (P3)
6.5.2.1 P0
Since the firmware for the microcontroller is located in a Flash memory device (for ease of
debugging and field upgradeability), and all memory and memory-mapped I/O are located
outside the microcontroller, P0 is used as a time-multiplexed low-order address and data bus. It
is not used for general I/O purposes.
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