SPSH4 Server SystemTechnical Product Specification
Revision 1.11
Intel reference number 10736
57
6.4 Board
Functions
This section describes functioning parts as required by the
Management Bus Architecture
Specification
and the
Enclosure Services SCSI Command Set
. In addition to these
requirements, the board is capable of downloading code via IMB to update the FLASH
executable code. The backplane functions begin at power-up. The microprocessor boots itself
via code residing in the FLASH boot block.
6.4.1 Reset
A cold reset occurs when power is cycled or the SCSI bus can be reset by a SAF-TE command.
6.4.2 Microcontroller
The microcontroller is a Philips* P80C652FBB operating at 12 MHz. The 80C652 is a derivative
of the 80C51 8-bit CMOS microcontroller. The 80C652 contains all of the features of the 80C51
(that is, the standard counter/timers T0 and T1, the standard serial I/O (UART), and four 8-bit
I/O ports).
The organization of the data memory is similar to the 80C51 except that the 80C652 has an
additional 128 bytes of RAM overlapped with the special function register space. This additional
RAM is addressed using indirect addressing only and is available as stack space.
The 80C652 is pin-for-pin compatible and code compatible with the 80C51, except for additional
Vss pins at the QFP package.
The features can be outlined as follows:
•
Operating frequency from 1.2 MHz to 16 MHz
•
80C51-based architecture
•
Four 8-bit I/O ports
•
Two 16-bit timer/counters
•
Full-duplex UART facilities
•
I
2
C Serial Interface
•
Two power control modes; idle mode, power-down mode
•
Operating temperature range: 0
°
C to +70
°
C
Summary of Contents for SPSH4 - Server Platform - 0 MB RAM
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