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Intel S1200V3RP, Technical Product Specification

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Platform Management Functional Overview 

Intel®

 Server Board S1200V3RP TPS 

 

 

Revision 1.2

62 

6.11.11

 

Alert Policy Table 

Associated with each PEF entry is an alert policy that determines which IPMI channel the alert 
is to be sent. There is a maximum of 20 alert policy entries. There are no pre-configured entries 
in the alert policy table because the destination types and alerts may vary by user. Each entry in 
the alert policy table contains four bytes for a maximum table size of 80 bytes. 

6.11.11.1

 

E-mail Alerting 

The Embedded Email Alerting feature allows the user to receive e-mails alerts indicating issues 
with the server. This allows e-mail alerting in an OS-absent (for example, Pre-OS and OS-Hung) 
situation. This feature provides support for sending e-mail by means of SMTP, the Simple Mail 
Transport Protocol as defined in Internet RC 821. The e-mail alert provides a text string that 
describes a simple description of the event. SMTP alerting is configured using the embedded 
web server. 

6.11.12

 

SM-CLP (SM-CLP Lite) 

SMASH refers to Systems Management Architecture for Server Hardware. SMASH is defined 
by a suite of specifications, managed by the DMTF, that standardize the manageability 
interfaces for server hardware. CLP refers to Command Line Protocol. SM-CLP is defined by 
the 

Server Management Command Line Protocol Specification (SM-CLP) ver1.0

, which is part 

of the SMASH suite of specifications. The specifications and further information on SMASH can 
be found at the DMTF website (

http://www.dmtf.org/

). 

The BMC provides an embedded 

lite

 version of SM-CLP that is syntax-compatible but not 

considered fully compliant with the DMTF standards.  

The SM-CLP utilized by a remote user by connecting a remote system using one of the system 
NICs. It is possible for third party management applications to create scripts using this CLP and 
execute them on server to retrieve information or perform management tasks such as reboot the 
server, configure events, and so on.  

The BMC embedded SM-CLP feature includes the following capabilities: 

 

Power on/off/reset the server. 

 

Get the system power state. 

 

Clear the System Event Log (SEL). 

 

Get the interpreted SEL in a readable format. 

 

Initiate/terminate a Serial Over LAN session. 

 

Support “help” to provide helpful information. 

 

Get/set the system ID LED. 

 

Get the system GUID. 

 

Get/set configuration of user accounts. 

 

Get/set configuration of LAN parameters. 

 

Embedded CLP communication should support SSH connection. 

 

Provide current status of platform sensors including current values. Sensors include 
voltage, temperature, fans, power supplies, and redundancy (power unit and fan 
redundancy). 

Summary of Contents for S1200V3RP

Page 1: ...Intel Server Board S1200V3RP Technical Product Specification Intel reference number G84364 004 Revision 1 2 January 2014 ...

Page 2: ...ovember 2012 0 5 Preliminary release May 2013 1 0 Updated BIOS Setup Interface Changed the chipset of S1200V3RPL to C226 October 2013 1 1 Updated Graphics Controller and Video output Changed the supporting OS for pGFX Display Port video output to Microsoft Windows 7 January 2014 1 2 Added Backup BIOS update instruction ...

Page 3: ... ARISING OUT OF DIRECTLY OR INDIRECTLY ANY CLAIM OF PRODUCT LIABILITY PERSONAL INJURY OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN MANUFACTURE OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS Intel may make changes to specifications and product descriptions at any time without notice Designers must not...

Page 4: ... 3 Post Error Codes 18 3 3 4 Processor Integrated I O Module IIO 18 3 3 5 Intel Integrated RAID Option 20 3 3 6 Optional I O Module Support 20 3 3 7 Intel I O Acceleration Technolgy 2 Intel I O AT2 21 3 4 Intel C220 series Chipset PCH Functional Overview 21 3 4 1 Digital Media Interface DMI 22 3 4 2 PCI Express Interface 22 3 4 3 Serial ATA SATA Controller 22 3 4 4 Low Pin Count LPC Interface 23 3...

Page 5: ...es 43 6 2 Basic and Advanced Features 44 6 3 Advanced Configuration and Power Interface ACPI 45 6 4 Power Control Sources 46 6 5 BMC Watchdog 46 6 6 Fault Resilient Booting FRB 47 6 7 Sensor Monitoring 47 6 8 Field Replaceable Unit FRU Inventory Device 48 6 9 System Event Log SEL 48 6 10 System Fan Management 48 6 10 1 Thermal and Acoustic Management 48 6 10 2 Thermal Sensor Input to Fan Speed Con...

Page 6: ...8 On board Connector Header Overview 75 8 1 Board Connector Information 75 8 2 Power Connectors 76 8 3 System Management Headers 77 8 3 1 Intel Remote Management Module 4 Dedicated NIC Connector 77 8 3 2 TPM connector 78 8 3 3 Intel ESRT2 RAID Upgrade Key Connector 78 8 3 4 Local Control Panel Header 78 8 3 5 HSBP_ I2 C Header 79 8 3 6 HDD LED Header 79 8 3 7 Chassis Intrusion Header 79 8 3 8 SATA...

Page 7: ... BIOS Flash Update 197 9 5 3 BIOS Backup Flash Update 198 9 6 BIOS Recovery 198 10 Jumper Blocks 201 10 1 BIOS Default Jumper Block 202 10 2 BIOS Recovery Jumper 202 10 3 Password Clear Jumper Block 203 10 4 Management Engine ME Firmware Force Update Jumper Block 204 10 5 BMC Force Update Jumper Block 205 11 Intel Light Guided Diagnostics 206 11 1 System ID LED 207 11 2 System Status LED 207 11 3 ...

Page 8: ...tage Immunity in Standy mode 215 13 1 9 Common Mode Noise 216 13 1 10 Ripple Noise 216 13 1 11 Timing Requirements 216 Appendix A Integration and Usage Tips 219 Appendix B Integrated BMC Sensor Tables 220 Appendix C POST Code Diagnostic LED Decoder 239 Appendix D POST Code Errors 245 Appendix E Supported Intel Server Chassis 252 Glossary 253 Reference Documents 256 ...

Page 9: ...Diagram 28 Figure 14 Setup Utility TPM Configuration Screen 36 Figure 15 Fan Speed Control Process 50 Figure 16 Intel RMM4 Lite Activation Key Installation 69 Figure 17 Intel RMM4 Dedicated Management NIC Installation 70 Figure 18 NIC1 with USB2 0 connector 88 Figure 19 NIC2 with USB3 0 connector 88 Figure 20 Main Screen 96 Figure 21 Advanced Screen 101 Figure 22 Processor Configuration Screen 104...

Page 10: ...t Manager Screen 189 Figure 45 Error Manager Screen 190 Figure 46 Save Exit Screen 192 Figure 47 Jumper Blocks J2K6 J2K8 J2K9 J3K2 J3K6 201 Figure 48 On Board LED Placement 206 Figure 49 Power Distribution Block Diagram 213 Figure 50 Differential Noise test setup 216 Figure 51 Output Voltage Timing 217 Figure 52 Turn On Off Timing Power Supply Signals 218 Figure 53 POST Code Diagnostic LEDs 239 Fi...

Page 11: ...Features 44 Table 16 ACPI Power States 45 Table 17 Power Control Initiators 46 Table 18 Fan Profiles 50 Table 19 Messaging Interfaces 52 Table 20 Factory Configured PEF Table Entries 61 Table 21 Diagnostic Data 67 Table 22 Additional Diagnostics on Error 67 Table 23 RMM4 Option Kits 69 Table 24 Enabling Advanced Management Features 70 Table 25 Board Connector Matrix 75 Table 26 Main Power Connecto...

Page 12: ...le 54 POST HotKeys Recognized 90 Table 55 BIOS Setup Page Layout 92 Table 56 BIOS Setup Keyboard Command Bar 93 Table 57 Screen Map 95 Table 58 Server Board Jumpers J2K6 J2K8 J2K9 J3K2 J3K6 202 Table 59 System Status LED State Definitions 207 Table 60 BMC Boot Reset Status LED Indicators 209 Table 61 Server Board Design Specifications 211 Table 62 MTBF Estimate 212 Table 63 Over Voltage Protection...

Page 13: ...Intel Server Board S1200V3RP TPS List of Tables Revision 1 2 xiii This page intentionally left blank ...

Page 14: ......

Page 15: ...erence Documents section for a list of available documents 1 1 Chapter Outline This document is divided into the following chapters Chapter 1 Introduction Chapter 2 Overview Chapter 3 Functional Architecture Chapter 4 System Security Chapter 5 Intel Technology Support Chapter 6 Platform Management Functional Overview Chapter 7 Advanced Management Feature Support RMM4 Chapter 8 On board Connector H...

Page 16: ...lding blocks are used together the fully integrated system will meet the intended thermal requirements of these components It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions Intel C...

Page 17: ... ECC and non ECC UDIMMs Chipset S1200V3RPO supports for Intel C224 Platform Controller Hub PCH chipset S1200V3RPS supports for Intel C222 Platform Controller Hub PCH chipset S1200V3RPL and S1200V3RPM support for Intel C226 Platform Controller Hub PCH chipset Cooling Fan Support Support for One processor fan 4 pin header Three front system fans 4 pin headers One rear system fan 4 pin header Add in ...

Page 18: ...n serial port B header One internal Type A USB 2 0 port One 9 pin USB header for eUSB SSD One 1x7 pin header for optional Intel Local Control Panel support One combined header consists of a 24 pin SSI EEB compliant front panel header Video Support Integrated 2D video controller Dual monitor video mode is supported 16 MB DDR3 Memory Only S1200V3RPM supports integrated graphics support for processor...

Page 19: ...ayout Figure 1 Intel Server Board S1200V3RP Layout 2 2 1 Server Board Connector and Component Layout The following figure shows the layout of the server board Each connector and major component is identified by a number or letter and a description is given in the figure below ...

Page 20: ...Overview Intel Server Board S1200V3RP TPS Revision 1 2 6 Figure 2 Intel Server Board S1200V3RPL and S1200V3RPS Layout ...

Page 21: ...Intel Server Board S1200V3RP TPS Overview Revision 1 2 7 Figure 3 Intel Server Board S1200V3RPO and S1200V3RPM Layout ...

Page 22: ...Overview Intel Server Board S1200V3RP TPS Revision 1 2 8 2 2 2 Server Board Mechanical Drawings Figure 4 Intel Server Board S1200V3RP Mounting Hole Locations ...

Page 23: ...Intel Server Board S1200V3RP TPS Overview Revision 1 2 9 Figure 5 Intel Server Board S1200V3RP Major Connector Pin 1 Locations ...

Page 24: ...Overview Intel Server Board S1200V3RP TPS Revision 1 2 10 Figure 6 Intel Server Board S1200V3RP Primary Side Keepout Zone ...

Page 25: ...ion 1 2 11 Figure 7 Intel Server Board S1200V3RP Second Side Keepout Zone 2 2 3 Server Board Rear I O Layout The following drawing shows the layout of the rear I O components for the server board Figure 8 Intel Server Board S1200V3RP Rear I O Layout ...

Page 26: ...3RPM use Intel C226 chipset The Intel Xeon Processor E3 1200 V3 Processors are made up of multi core processors based on the 22nm processor technology The 4th Intel Core i3 Processors are made up of dual core processors based on the 22nm processor technology This chapter provides a high level description of the functionality associated with each chipset component and the architectural blocks that ...

Page 27: ...d at http serverconfigurator intel com sct_app aspx 3 2 Processor Function Overview With the release of the Intel Xeon processor E3 1200 V3 product family several key system components including the CPU Integrated Memory Controller IMC and Integrated IO Module IIO have been combined into a single processor package and feature up to 16 lanes of Gen 3 PCI Express links The FMA instruction has improv...

Page 28: ...hannel and dual channel memory organization modes Data burst length of eight cycles for all memory organization modes Memory DDR3 data transfer rates of 1333 and 1600 MT s 64 bit wide channels DDR3L I O Voltage of 1 35 V Theoretical maximum memory bandwidth of 21 3 GB s in dual channel mode assuming 1333 MT s 25 6 GB s in dual channel mode assuming 1600 MT s 1 Gb 2 Gb and 4 Gb DDR3L DRAM device te...

Page 29: ... support for RDIMMs 2 No support for SODIMM 3 All channels in a system run at the fastest common frequency 4 Mixing ECC and non ECC UDIMMs anywhere on the platform is not supported 5 Static CLTT supported using BMC requires ECC DIMMs with thermal sensor 3 3 1 1 Memory Population Rules Note Although mixed DIMM configurations are supported Intel only performs platform validation on systems that are ...

Page 30: ...ckets is detailed in the following table Table 3 Intel Server Board S1200V3RP DIMM Nomenclature 0 Channel A 1 Channel B A1 A2 B1 B2 Figure 10 Intel Server Board S1200V3RP DIMM Slot Layout Table 4 Intel Server Board S1200V3RP DIMM Maximum Configuration Max Memory Possible 1Gb DRAM Technology 2Gb DRAM Technology 4Gb DRAM Technology Single Rank UDIMM 4GB 4 x 1GB DIMMs 8GB 4 x 2GB DIMMs 16GB 4 x 4GB D...

Page 31: ...ode 4 Memory Mapped I O MMIO 5 Manageability Engine ME 6 BIOS flash 3 3 2 Memory RAS Features For Intel Server Board S1200V3RP product family the form of Memory RAS provided is Error Correction Code ECC ECC uses extra bits 64 bit data in a 72 bit DRAM array to add an 8 bit calculated Hamming Code to each 64 bits of data This additional encoding enables the memory controller to detect and report si...

Page 32: ...d size ECC capability and in which memory slot the DIMMs are installed An invalid configuration will cause the system to halt 0xEA Channel Training Error If the memory initialization process is unable to properly perform the Data Data Strobe timing training on a memory channel the BIOS emits a beep code and displays POST Diagnostic LED code 0xEA momentarily during the beeping If there is usable me...

Page 33: ...I Express Gen2 x1 PCI Express Gen2 x8 PCI Express Gen3 x8 S1200V3RPL Slot4 Slot7 Slot5 Slot6 SAS Module PCI Express Gen2 x4 PCI Express Gen2 x1 No card installed PCI Express Gen3 x8 or Gen2 x16 No Card installed PCI Express Gen3 x8 PCI Express Gen2 x8 PCI Express Gen2 x8 PCI Express Gen3 x8 No Card installed PCI Express Gen2 x4 Gen3 x8 PCI Express Gen2 x4 S1200V3RPO S1200V3RPM Slot6 IO Module SAS ...

Page 34: ...al support for Intel RAID Maintenance Free Backup Units AXXRMFBU2 or improved Lithium Polymer battery Table 6 Supported Intel Integrated RAID Modules External Name Description Product Code Intel Integrated RAID Module RMS25CB080 8 Port SAS 2 1 Full HW RAID 1GB IOM Slot RAID Levels 0 1 10 5 50 6 60 RMS25CB080 Intel Integrated RAID Module RMS25CB040 4 Port SAS 2 1 Full HW RAID 1GB IOM Slot RAID Leve...

Page 35: ... Ethernet Controller USB 2 0 TPM GbE GbE FLASH DRAM SERIAL 2 On Standby Misc VRs Back Panel Back Panel Front Panel Header Back Panel Back Panel PCIe Gen1 x1 P7 P6 P5 PCIe Gen1 x1 PCIe Gen1 x1 SPI Back Panel USB 3 0 SGPIO Slot 4 x8 connector P1 P2 P3 P4 RGMII DNM Intel I210 Gigabit Ethernet Controller P8 Slot 7 PCIe Gen2 x4 PCIe Gen2 x1 x4 or x8 connector 2 USB USB Front Panell USB 3 0 Header Type ...

Page 36: ...to support one Gen2 x1 port widths of slot 7 On the Intel Server Boards S1200V3RP family product PCI Express Root Port 5 is configured to support one Gen1 x1 widths connection with the BMC chip PCI Express Root Port 5 and 6 are configured to support two Gen1 x1 widths connection with the two Intel I210 Gigabit Ethernet Network controller 3 4 3 Serial ATA SATA Controller The Intel C220 series chips...

Page 37: ...RAID 0 1 5 and 10 functionality on up to 6 SATA ports of the Intel C220 series chipset RSTe RAID support is provided to allow multiple RAID levels to be combined on a single set of hard drives such as RAID 0 and RAID 1 on two disks Other RAID features include hot spare support SMART alerting and RAID 0 auto replace Software components include an Option ROM for pre boot configuration and boot funct...

Page 38: ...0 USB 3 4 USB3 0 J1J1 USB 5 6 USB3 0 J1J4 USB 7 USB2 0 Type A J1K3 USB 8 9 USB2 0 J5K1 eUSB USB2 0 S1200V3RPL S1200V3RPO S1200V3RPM Yes Yes Yes Yes Yes Yes S1200V3RPS Yes Yes No Yes Yes Yes 3 4 6 1 Native USB Support During the power on self test POST the BIOS initializes and configures the USB subsystem The BIOS can initialize and use the following types of USB devices USB Specification compliant...

Page 39: ...0 1000 Mb Ethernet ports The Intel Ethernet Controller I210 is single compact low power components that offer a fully integrated Gigabit Ethernet Media Access Control MAC and Physical Layer PHY port The Intel Ethernet Controller I210 uses the PCI Express architecture from the Intel C220 series PCH and provides a single port implementation in a relatively small area so it can be used for server and...

Page 40: ...anagement The Intel C220 series chipset s power management functions include enhanced clock control and various low power suspend states for example Suspend to RAM and Suspend to Disk A hardware based thermal management circuit permits software independent entrance to low power states The Intel C220 series chipset contains full support for the Advanced Configuration and Power Interface ACPI Specif...

Page 41: ...m Management Bus SMBus Specification Version 2 0 Quick Command Send Byte Receive Byte Write Byte Word Read Byte Word Process Call Block Read Write and Host Notify The Intel C220 series chipset s SMBus also implements hardware based Packet Error Checking for data robustness and the Address Resolution Protocol ARP to dynamically provide address to all SMBus devices 3 4 12 Intel Virtualization Techno...

Page 42: ...Functional Architecture Intel Server Board S1200V3RP TPS Revision 1 2 28 Figure 12 Integrated Baseboard Management Controller BMC Overview Figure 13 Integrated BMC Functional Block Diagram ...

Page 43: ...functionality that allows various events to power on and power off the system 3 5 2 Graphics Controller and Video Support The integrated graphics controller provides support for the following features as implemented on the server board Integrated Graphics Core with 2D Hardware accelerator DDR 3 memory interface supporting up to 128MB of memory 16MB allocated to graphic Supports display resolutions...

Page 44: ...eration Intel Clear Video Technology HD Support is a collection of video playback and enhancement features that improve the end user s viewing experience Encode transcode HD content Playback of high definition content including Blu ray Disc Superior image quality with sharper more colorful images Playback of Blu ray disc S3D content using HDMI 1 4a specification compliant with 3D DirectX Video Acc...

Page 45: ...ix general purpose timers Interrupt controller Multiple SPI flash interfaces NAND Memory interface Sixteen mailbox registers for communication between the BMC and host LPC ROM interface BMC watchdog timer capability SD MMC card controller with DMA support LED support with programmable blink rate controls on GPIOs Port 80h snooping capability Secondary Service Processor SSP which provides the HW ca...

Page 46: ...work interfaces These interfaces are not shared with the host system At any time only one dedicated interface may be enabled for management traffic The default active interface is the NIC 1 port For these channels support can be enabled for IPMI over LAN and DHCP For security reasons embedded LAN channels have the following default settings IP Address Static All users disabled ...

Page 47: ...d a popup warning message will be displayed although the weak password will be accepted Once set a password can be cleared by changing it to a null string This requires the Administrator password and must be done through BIOS Setup or other explicit means of changing the passwords Clearing the Administrator password will also clear the User password Alternatively the passwords can be cleared by us...

Page 48: ...TPM and is secured from external software attacks and physical theft A pre boot environment such as the BIOS and operating system loader uses the TPM to collect and store unique measurements from multiple factors within the boot process to create a system fingerprint This unique fingerprint remains the same unless the pre boot environment is tampered with Therefore it is used to compare to future ...

Page 49: ...he TPM commands 4 2 3 TPM Security Setup Options The BIOS TPM Setup allows the operator to view the current TPM state and to carry out rudimentary TPM administrative operations Performing TPM administrative options through the BIOS setup requires TPM physical presence verification Using BIOS TPM Setup the operator can turn ON or OFF TPM functionality and clear the TPM ownership contents After the ...

Page 50: ...h the security screen To access this screen from the Main screen select the Security option Figure 14 Setup Utility TPM Configuration Screen Table 12 TPM Setup Utility Security Configuration Screen Fields Setup Item Options Help Text Comments TPM State Enabled and Activated Enabled and Deactivated Disabled and Activated Disabled and Deactivated Information only Shows the current TPM device state A...

Page 51: ...rm components When used in conjunction with Intel Virtualization Technology Intel Trusted Execution Technology provides hardware rooted trust for your virtual applications This hardware rooted security provides a general purpose safer computing environment capable of running a wide variety of operating systems and applications to increase the confidentiality and integrity of sensitive information ...

Page 52: ...cerned I O hardware assist features complementary to but independent of VT d Intel VT x is designed to support multiple software environments sharing same hardware resources Each software environment may consist of OS and applications The Intel Virtualization Technology features can be enabled or disabled in the BIOS setup The default behavior is disabled Intel VT d is supported jointly by the Int...

Page 53: ...of hot spots Control capability that reduces platform power consumption to protect a server in a hot spot Ability to monitor server inlet temperatures to enable greater rack utilization in areas with adequate cooling The requirements listed above are those that are addressed by the Intel C220 series chipset Management Engine ME and Intel Intelligent Power Node Manager NM technology The ME NM combi...

Page 54: ...n information Processor Power monitoring and limiting The ME NM monitors processor or socket power consumption and holds average power over duration It can be queried to return actual power at any given instant The monitoring process of the ME will be used to limit the processor power consumption through processor P states and dynamic core allocation Core allocation at boot time Restrict the numbe...

Page 55: ...and alert 5 3 1 Hardware Requirements NM is supported only on platforms that have the NM FW functionality loaded and enabled on the Management Engine ME in the SSB and that have a BMC present to support the external LAN interface to the ME NM power limiting feature requires a means for the ME to monitor input power consumption for the platform This capability is generally provided by means of PMBu...

Page 56: ...ich the server board is integrated and any additional system level components and options that may be installed 6 1 1 IPMI 2 0 Features Baseboard management controller BMC IPMI Watchdog timer Messaging support including command bridging and user session support Chassis device functionality including power reset control and BIOS boot flags support Event receiver device The BMC receives and processe...

Page 57: ...net Controller Thermal Monitoring Global Aggregate Temperature Margin Sensor Platform environment control interface PECI thermal management support Memory Thermal Management DIMM temperature monitoring New sensors and improved acoustic management using closed loop fan control algorithm taking into account DIMM temperature readings Power supply redundancy monitoring and support Power unit managemen...

Page 58: ...edded platform debug feature which allows capture of detailed data for later analysis Provisioning and inventory enhancements Inventory data system information export partial SMBIOS table DCMI 1 1 compliance product specific Management support for PMBus rev1 2 compliant power supplies Energy Star Server Support Smart Ride Through SmaRT Closed Loop System Throttling CLST Power Supply Cold Redundanc...

Page 59: ...upported Description S0 Yes Working The front panel power LED is on not controlled by the BMC The fans spin at the normal speed as determined by sensor inputs Front panel buttons work normally S1 Yes Sleeping Hardware context is maintained equates to processor and chipset clocks being stopped The front panel power LED blinks at a rate of 1 Hz with a 50 duty cycle not controlled by the BMC The watc...

Page 60: ...er This feature is comprised of a set of capabilities whose purpose is to detect misbehaving subsections of BMC firmware the BMC CPU itself or HW subsystems of the BMC component and to take appropriate action to restore proper operation The action taken is dependent on the nature of the detected failure and may result in a restart of the BMC CPU one or more BMC HW subsystems or a restart of malfun...

Page 61: ...ta bytes The BMC then hard resets the system assuming the BIOS selected reset as the watchdog timeout action The BIOS is responsible for disabling the FRB2 timeout before initiating the option ROM scan and before displaying a request for a boot password If the processor fails and causes an FRB2 timeout the BMC resets the system The BIOS gets the watchdog expiration status from the BMC If the statu...

Page 62: ...of Space IPMI completion code C4h Events logged to the SEL can be viewed using Intel s SELVIEW utility Embedded Web Server and Active System Console 6 10 System Fan Management The BMC controls and monitors the system fans Each fan is associated with a fan speed sensor that detects fan failure and may also be associated with a fan presence sensor for hot swap support For redundant fan configuration...

Page 63: ... depends on the actual thermal characters of a specific system Refer to Intel Server System R1000RP product family Technical Product Specification and Intel Server System P4000RP product family Technical Product Specification for system thermal and acoustic management 6 10 2 Thermal Sensor Input to Fan Speed Control The BMC uses various IPMI sensors as input to the fan speed control Some of the se...

Page 64: ...ess 6 10 3 Fan Profiles The server system supports multiple fan control profiles to support acoustic targets and American Society of Heating Refrigerating and Air Conditioning Engineers ASHRAE compliance The BIOS Setup utility can be used to choose between meeting the target acoustic level or enhanced system performance This is accomplished through fan profiles The BMC supports eight fan profiles ...

Page 65: ...ults to open loop thermal throttling OLTT In the OLTT mode it is assumed that the DIMM temperature sensors are not available for fan speed control Throttling levels are changed dynamically to cap throttling based on memory and system thermal conditions as determined by the system and DIMM power and thermal parameters The BMC s fan speed control functionality is linked to the memory throttling mech...

Page 66: ...assigned an IPMI channel ID by IPMI 2 0 The following table shows the standard channel assignments Table 19 Messaging Interfaces Channel ID Interface Supports Sessions 0 Primary IPMB No 1 LAN 1 Yes 2 LAN 2 Yes 3 LAN3 1 Provided by the Intel Dedicated Server Management NIC Yes 4 Reserved Yes 5 USB 2 No 6 Secondary IPMB No 7 SMM No 8 0Dh Reserved 0Eh Self 3 0Fh SMS Receive Message Queue No Notes 1 O...

Page 67: ...nd local area network LAN communication between the BMC and the network See the Intelligent Platform Management Interface Specification Second Generation v2 0 for details about the IPMI over LAN protocol Run time determination of LAN channel capabilities can be determined by both standard IPMI defined mechanisms 6 11 3 1 RMCP ASF Messaging The BMC supports RMCP ping discovery in which the BMC resp...

Page 68: ...e PHY on the RMM4 connects to the BMC s other RMII RGMII interface that is the one that is not connected to the baseboard NICs This BMC port is configured for RGMII usage In addition to the use of an RMM4 add in card for a dedicated management channel on systems that support multiple Ethernet ports on the baseboard the system BIOS provides a setup option to allow one of these baseboard ports to be...

Page 69: ... the server board supports IPv6 for manageability channels Configuration of IPv6 is provided by extensions to the IPMI Set and Get LAN Configuration Parameters commands as well as through a Web Console IPv6 configuration web page The BMC supports IPv4 and IPv6 simultaneously so they are both configured separately and completely independently For example IPv4 can be DHCP configured while IPv6 is st...

Page 70: ...s well as the BMC s Embedded UI allowing for user to specify the physical LAN links constitute the redundant network paths or physical LAN links constitute different network paths BMC supports only an all or nothing approach that is all interfaces bonded together or none are bonded together The LAN Failover feature applies only to BMC LAN traffic It bonds all available Ethernet devices but only on...

Page 71: ... the following network safety precautions 1 The user may only set a subnet mask that is valid per IPv4 and RFC 950 Internet Standard Subnetting Procedure Invalid subnet values return a 0xCC Invalid Data Field in Request completion code and the subnet mask is not set If no valid mask has been previously set default subnet mask is 0 0 0 0 2 The user may only set a default gateway address that can po...

Page 72: ...ent users from disrupting the BMC s LAN configuration the BMC treats these parameters as read only while DHCP is enabled for the associated LAN channel Using the Set LAN Configuration Parameter command to attempt to change one of these parameters under such circumstances has no effect and the BMC returns error code 0xD5 Cannot Execute Command Command or request parameter s are not supported in pre...

Page 73: ...as defined by IPMI 2 0 specifications VLAN is supported internally by the BMC not through switches VLAN provides a way of grouping a set of systems together so that they form a logical network This feature can be used to set up a management VLAN where only devices which are members of the VLAN will receive packets related to management and members of the VLAN will be isolated from any other networ...

Page 74: ... suitable for LAN 6 11 7 Secure Shell SSH Secure Shell SSH connections are supported for SMASH CLP sessions to the BMC 6 11 8 Serial over LAN SOL 2 0 The BMC supports IPMI 2 0 SOL IPMI 2 0 introduced a standard serial over LAN feature This is implemented as a standard payload type 01h over RMCP Three commands are implemented for SOL 2 0 configuration Get SOL 2 0 Configuration Parameters and Set SO...

Page 75: ...system boot event System restart reboot 12 Drive Failure Predicted Failure Hot Swap Controller Additionally the BMC supports the following PEF actions Power off Power cycle Reset OEM action Alerts The Diagnostic interrupt action is not supported 6 11 10 LAN Alerting The BMC supports sending embedded LAN alerts called SNMP PET Platform Event traps and SMTP email alerts The BMC supports a minimum of...

Page 76: ...or server hardware CLP refers to Command Line Protocol SM CLP is defined by the Server Management Command Line Protocol Specification SM CLP ver1 0 which is part of the SMASH suite of specifications The specifications and further information on SMASH can be found at the DMTF website http www dmtf org The BMC provides an embedded lite version of SM CLP that is syntax compatible but not considered f...

Page 77: ...Encryption using 128 bit SSL is supported User authentication is based on user id and password The GUI presented by the embedded web server authenticates the user before allowing a web session to be initiated It presents all functions to all users but grays out those functions that the user does not have privilege to execute For example if a user does not have privilege to power control the item w...

Page 78: ... is provided through a configuration option in the UI Display of processor and memory information as is available over IPMI over LAN Ability to get and set Node Manager NM power policies Display of power consumed by the server Ability to view and configure VLAN settings Warn user the reconfiguration of IP address will cause disconnect Capability to block logins for a period of time after several c...

Page 79: ...lect in EWS during automatic manual EWS sync up with BMC Virtual Front Panel help is available for virtual panel module At present NMI button in VFP is disabled It can be used in future 6 11 15 Embedded Platform Debug The Embedded Platform Debug feature supports capturing low level diagnostic data applicable MSRs PCI config space registers and so on This feature allows a user to export this data i...

Page 80: ... power supply The BMC copies board and system serial numbers and part numbers into the power supply whenever a new power supply is installed in the system or when the system is first powered on This information is included as part of the power supply black box data for each installed power supply Accessibility through IPMI interfaces The platform debug file can be accessed using an external IPMI i...

Page 81: ... bytes of PCI config data for each PCI device PCI error registers MSR registers MCH registers 6 11 16 Data Center Management Interface DCMI The DCMI Specification is an emerging standard that is targeted to provide a simplified management interface for Internet Portal Data Center IPDC customers It is expected to become a requirement for server platforms which are targeted for IPDCs DCMI is an IPMI...

Page 82: ... LDAP server for login authentication This is only supported for non IPMI logins including the embedded web UI and SM CLP IPMI users passwords and sessions are not supported over LDAP LDAP can be configured IP address of LDAP server port and so on using the BMC s Embedded Web UI LDAP authentication and authorization is supported over the any NIC configured for system management The BMC uses a stan...

Page 83: ...ted Server Management NIC DMN Table 23 RMM4 Option Kits Product Code Description Kit Contents Benefits AXXRMM4LITE Intel Remote Management Module 4 Lite RMM4 Lite Activation Key Enables KVM and media redirection from the onboard NIC AXXRMM4 Intel Remote Management Module 4 RMM4 Lite Activation Key Dedicated NIC Port Module Dedicated NIC for management traffic Higher bandwidth connectivity for KVM ...

Page 84: ...VM and media Redirection with 1Gbe NIC If the optional Dedicated Server Management NIC is not used then the traffic can only go through the onboard Integrated BMC shared NIC and will share network bandwidth with the host system Advanced manageability features are supported over all NIC ports enabled for server manageability 7 1 Keyboard Video and Mouse KVM Redirection The BMC firmware supports key...

Page 85: ...mouse Compression of the redirected screen Ability to select a mouse configuration based on the OS type Supports user definable keyboard macros KVM redirection feature supports the following resolutions and refresh rates 640x480 at 60Hz 72Hz 75Hz 85Hz 100Hz 800x600 at 60Hz 72Hz 75Hz 85Hz 1024x768 at 60Hx 72Hz 75Hz 85Hz 1280x960 at 60Hz 1280x1024 at 60Hz 1600x1200 at 60Hz 1920x1080 1080p 1920x1200 ...

Page 86: ...e KVM session is available even when the server is powered off in stand by mode No re start of the remote KVM session is required during a server reset or power on off A BMC reset for example due to a BMC Watchdog initiated reset or BMC reset after BMC FW update requires the session to be re established KVM sessions persist across system reset but not across an AC power loss 7 1 5 Usage As the ser...

Page 87: ... on the client s capabilities A remote media session is maintained even when the server is powered off in standby mode No restart of the remote media session is required during a server reset or power on off A BMC reset for example due to a BMC reset after BMC FW update requires the session to be re established The mounted device is visible to and useable by managed system s OS and BIOS in both pr...

Page 88: ...Advanced Management Feature Support RMM4 Intel Server Board S1200V3RP TPS Revision 1 2 74 5124 CD Redirection Secure 5127 FD Redirection Secure 7578 Video Redirection 7582 Video Redirection Secure ...

Page 89: ...PU 1 U6F1 CPU sockets 1150 Main memory 4 J7C1 J8C1 J8C2 J9C2 DIMM sockets 240 PCI Express x8 mechanical 3 J1B1 J2B1 J4B1 Card edge 98 PCI Express x16 mechanical 1 J3B1 Card edge 164 Intel RMM4 NIC 1 J4C1 Connector 30 Intel RMM4 Lite 1 J4B1 Connector 7 SATA Key to enable ESRT2 RAID5 1 J4A1 Header 4 System fans 4 J3K4 J8K1 J8K2 J8B1 Header 4 CPU fan 1 J7K1 Header 4 Battery 1 BT2E1 Battery holder 2 S...

Page 90: ...nnectors The main power supply connection uses an SSI compliant 2x12 pin connector J9H1 Two additional power related connectors also exist One SSI compliant 2x4 pin power connector J9B1 to provide 12 V power to the CPU voltage regulators and memory One SSI compliant 1x5 pin connector J9C3 to provide I2C monitoring of the power supply The following tables define these connector pin outs Table 26 Ma...

Page 91: ...ystem Management Headers 8 3 1 Intel Remote Management Module 4 Dedicated NIC Connector A 30 pin Intel RMM4 connector J4C1 and a 7 pin Intel RMM4 Lite connector J4B1 are included on the server board to support the optional Intel Remote Management Module 4 dedicated NIC module This server board does not support third party management cards Note This connector is not compatible with the previous gen...

Page 92: ...LPC_FRAME_N 7 P3V3 8 GND 9 RST_IBMC_NIC_N 10 CLK_33M_TPM_CONN 11 LPC_LAD 3 12 GND 13 GND 14 LPC_LAD 2 8 3 3 Intel ESRT2 RAID Upgrade Key Connector The server board provides one connector to support Intel ESRT2 RAID Upgrade Key The I Upgrade Key is a small PCB board that enables RAID 5 software stack of ESRT2 SW RAID The pin configuration of connector is identical and defined in the following table...

Page 93: ... chassis intrusion header which can be used when the chassis is configured with a chassis intrusion switch The header has the following pin out Table 36 Chassis Intrusion Header Pin out J1F1 Header State Description Pins 1 and 2 closed FM_INTRUDER_HDR_N is pulled HIGH Chassis cover is closed Pins 1 and 2 open FM_INTRUDER_HDR_N is pulled LOW Chassis cover is removed 8 3 8 SATA SGPIO Header SGPIO us...

Page 94: ...ector Pin out J1E1 Pin Signal Pin Signal 1 SB3 3V 2 SB3 3V 3 Key 4 SB5V 5 Power LED Cathode 6 System ID LED Cathode 7 3 3V 8 System Fault LED Anode 9 HDD Activity LED Cathode 10 System Fault LED Cathode 11 Power Switch 12 NIC 1 1 2 Activity LED 13 GND Power Switch 14 NIC 1 1 2 Link LED 15 Reset Switch 16 I2C SDA 17 GND Reset ID NMI Switch 18 I2C SCL 19 System ID Switch 20 Chassis Intrusion 21 Pull...

Page 95: ...the LED to blink for 15 seconds 8 4 3 System Reset Button Support When pressed this button will reboot and re initialize the system 8 4 4 NMI Button Support When the NMI button is pressed it puts the server in a halt state and causes the BMC to issue a non maskable interrupt NMI This can be useful when performing diagnostics for a given issue where a memory download is necessary to help determine ...

Page 96: ...shows the current health of the server system The system provides two locations for this feature one is located on the Front Control Panel the other is located on the back edge of the server board viewable from the back of the system Both LEDs are tied together and will show the same state The System Status LED states are driven by the on board platform management sub system 8 5 I O Connectors 8 5...

Page 97: ... 13 GND Ground 14 GND Ground 15 I O AUX_CH P 16 GND Ground 17 I O AUX_CH N 18 IN HOT PLUG DETECT 19 PWR RTN RETURN DP_PWR 20 PWR OUT DP_PWR 8 5 3 SATA Connectors The server board provides up to 6 SATA connectors SATA 0 J1K4 SATA 1 J1K1 SATA 2 J1K5 SATA 3 J1K2 SATA 4 J2K5 and SATA 5 J2K3 The pin configuration for each connector is identical and defined in the following table Table 44 SATA Connector...

Page 98: ...send 5 SPB_OUT_N TXD Transmit data 6 SPB_CTS CTS clear to send 7 SPB_DTR DTR Data terminal ready 8 SPB_RI RI Ring indicate 9 GND Ground 10 KEY PIN No pin 8 5 5 USB Connector One 2x5 connectors on the server board J1K3 provides support for two additional USB 2 0 ports J1K3 is recommended for front panel USB ports Table 47 Internal USB2 0 Connector Pin out J1K3 Pin Signal Name Description 1 USB_PWR_...

Page 99: ...eed Tx 15 IntA_P2_SSTX USB3 ICC Port2 Super Speed Tx 16 GND Ground 17 IntA_P2_SSRX USB3 ICC Port2 SuperSpeed Rx 18 IntA_P2_SSRX USB3 ICC Port2 SuperSpeed Rx 19 Vbus Power 20 KEY PIN No pin The server board includes one 10 pin 2mm low profile connector J5K1 on the server boards provides an option to support a low profile eUSB Solid State Drive Table 49 Pin out of Internal Low Profile USB Connector ...

Page 100: ...D _ACT_N 19 RSVD_PIN19 20 RPESENT_N 21 RSVD_PIN21 22 WAKE_N 23 GND 24 RESET_N 25 SMB_3V3SB_CLK 26 GND 27 SMB_3V3SB_DAT 28 CLK_100M_DP 29 GND 30 CLK_100M_DN 31 PE_TN_7 32 GND 33 PE_TP_7 34 PE_RN_7 35 GND 36 PE_RP_7 37 PE_TN_6 38 GND 39 PE_TP_6 40 PE_RN_6 41 GND 42 PE_RP_6 43 PE_TN_5 44 GND 45 PE_TP_5 46 PE_RN_5 47 GND 48 PE_RP_5 49 PE_TN_4 50 GND 51 PE_TP_4 52 PE_RN_4 53 GND 54 PE_RP_4 55 PE_TN_3 5...

Page 101: ...19 PE_TN_5 20 GND 21 GND 22 PE_RP_5 23 PE_TP_4 24 PE_RN_5 25 PE_TN_4 26 GND 27 GND 28 PE_RP_4 29 PE_TP_3 30 PE_RN_4 31 PE_TN_3 32 GND 33 GND 34 PE_RP_3 35 PE_TP_2 36 PE_RN_3 37 PE_TN_2 38 GND 39 GND 40 PE_RP_2 41 PE_TP_1 42 PE_RN_2 43 PE_TN_1 44 GND 45 GND 46 PE_RP_1 47 PE_TP_0 48 PE_RN_1 49 PE_TN_0 50 GND 51 GND 52 PE_RP_0 53 SMD_3V3SB_DAT 54 PE_RN_0 55 SMD_3V3SB_CLK 56 GND 57 GND 58 RESET_N 59 R...

Page 102: ...Overview Intel Server Board S1200V3RP TPS Revision 1 2 88 8 5 8 NIC1 with USB2 0 connector Location JA6A1 Figure 18 NIC1 with USB2 0 connector 8 5 9 NIC2 with USB3 0 connector Location JA5A1 Figure 19 NIC2 with USB3 0 connector ...

Page 103: ...Out FAN_TACH signal is connected to the BMC to monitor the fan speed FAN_PWM signal to control fan speed 4 Fan PWM Fan Tach Out In FAN_PWM signal to control fan speed FAN_TACH signal is connected to the BMC to monitor the fan speed Note Intel Corporation server boards support peripheral components and can contain a number of high density VLSI and power delivery components that need adequate airflo...

Page 104: ...se Stop POST temporarily 9 2 POST Logo Diagnostic Screen The logo Diagnostic Screen displays in one of two forms If Quiet Boot is enabled in the BIOS setup a logo splash screen displays By default Quiet Boot is enabled in the BIOS setup If the logo displays during POST press Esc to hide the logo and display the diagnostic screen If a logo is not present in the flash ROM or if Quiet Boot is disable...

Page 105: ...rror manager The BIOS Setup interface consists of a number of pages or screens Each page contains information or links to other pages The advanced tab in Setup displays a list of general categories as links These links lead to pages containing a specific category s configuration The following sections describe the look and behavior for the platform setup 9 4 1 BIOS Setup Operation The BIOS Setup U...

Page 106: ...ulti level hierarchy of pages beneath one of the top level Tabs the Page Title identifying the specific page which the user is viewing is located in the upper left corner of the page Using the ESC Escape key will return the user to the higher level in the hierarchy until the top level Tab page is reached Setup Item List The Setup Item List is a set of control entries and informational items The li...

Page 107: ...lue field contains configurable parameters Depending on the security option chosen and in effect by the password a menu feature s value may or may not be changed If a value cannot be changed its field is made inaccessible and appears grayed out Table 56 BIOS Setup Keyboard Command Bar Key Option Description Enter Execute Command The Enter key is used to activate submenus when the selected feature ...

Page 108: ...ghlighted and Enter is pressed all changes are saved and the Setup is exited If No is highlighted and Enter is pressed or the Esc key is pressed the user is returned to where they were before F10 was pressed without affecting any existing values 9 4 1 4 Setup Screen Menu Selection Bar The Setup Screen Menu selection bar is located at the top of the BIOS Setup Utility screen It displays tabs showin...

Page 109: ...and reboot to take place in order for the changes to take effect Alternatively pressing ESC discards the changes and resumes POST to continue to boot the system according to the boot order set from the last boot 9 4 2 1 Map of Screens and Functionality There are a number of screens in the entire Setup collection They are organized into major categories Each category has a hierarchy beginning with ...

Page 110: ...ns Screen Tab CDROM Order Hard Disk Order Floppy Order Network Device Order BEV Device Order Add EFI Boot Option Delete EFI Boot Option Boot Manager Screen Tab Error Manager Screen Tab Save Exit Screen Tab 9 4 2 2 Main Screen Tab The Main Screen is the first screen that appears when the BIOS Setup configuration utility is entered unless an error has occurred If an error has occurred the Error Mana...

Page 111: ...have that limitation In some cases this means that the Platform ID is abbreviated from the marketing designation Back to Main Screen Screen Map 3 System Booted From Option Values Primary Backup Help Text None Comments Information only Displays the exact BIOS portion on the board which is executing POST Boot from Backup BIOS means the BIOS is running in Recovery mode and the Primary BIOS may be cor...

Page 112: ...ional on the board The version information displayed is taken from the BIOS ID String with the timestamp segment dropped off The segments displayed are Platform Identifies that this is the correct platform BIOS 86B Identifies this BIOS as being an Intel Server BIOS xx Major Revision level of the BIOS yy Release Revision level for this BIOS zzzz Release Number for this BIOS Back to Main Screen Scre...

Page 113: ...n is enabled the Quiet Boot setting is disregarded and the text mode Diagnostic Screen is displayed unconditionally Back to Main Screen Screen Map 9 POST Error Pause Option Values Enabled Disabled Help Text Enabled Go to the Error Manager for critical POST errors Disabled Attempt to boot and do not go to the Error Manager for critical POST errors Comments If enabled the POST Error Pause option tak...

Page 114: ...ents This field will initially display the current system time 24 hour time It may be edited to change the system time When the System Time is reset by the BIOS Defaults jumper BIOS Recovery Flash Update or other method the time will be the earliest time of day in the allowed range 00 00 00 although the time will be updated beginning from when it is reset early in POST Back to Main Screen Screen M...

Page 115: ...go to the Processor Configuration group of configuration settings Back to Advanced Screen Screen Map 2 Memory Configuration Option Values None Help Text View Configure memory information and settings Comments Selection only Select this line and press the Enter key to go to the Memory Configuration group of configuration settings Back to Advanced Screen Screen Map 3 Mass Storage Controller Configur...

Page 116: ...en Screen Map 5 Serial Port Configuration Option Values None Help Text View Configure serial port information and settings Comments Selection only Select this line and press the Enter key to go to the Serial Port Configuration group of configuration settings Back to Advanced Screen Screen Map 6 USB Configuration Option Values None Help Text View Configure USB information and settings Comments Sele...

Page 117: ...settings Back to Advanced Screen Screen Map 9 4 2 4 Processor Configuration The Processor Configuration screen displays the processor identification and microcode level core frequency cache sizes information for all processors currently installed It also allows the user to enable or disable a number of processor options To access this screen from the Main screen select Advanced Processor Configura...

Page 118: ...figuration Screen Screen Field Descriptions 1 Processor ID Option Values CPUID Help Text None Comments Information only Displays the Processor Signature value from the CPUID instruction identifying the type of processor and the stepping S1200V3RP series boards have a single Processor ID display ...

Page 119: ...ced Screen Screen Map 4 L1 Cache RAM Option Values L1 cache size Help Text None Comments Information only Displays size in KB of the processor L1 Cache Since L1 cache is not shared between cores this is shown as the amount of L1 cache per core There are two types of L1 cache so this amount is the total of L1 Instruction Cache plus L1 Data Cache for each core Back to Advanced Screen Screen Map 5 L2...

Page 120: ...ng from processor Help Text None Comments Information only Displays Brand ID string read from processor with CPUID instruction Back to Advanced Screen Screen Map 8 CPU Core Ratio Option Values 0 63 Help Text Enter Core Ratio Multiplier 0 63 Comments In order for this option to be available Show CPU Core Ratio must be Enabled Back to Advanced Screen Screen Map 9 Show CPU Core Ratio Option Values En...

Page 121: ...ltage and core frequency which can result in decreased average power consumption and decreased average heat production Contact your OS vendor regarding OS support of this feature Comments When Disabled the processor setting reverts to running at Max TDP Core Frequency rated frequency This option is only visible if all processors installed in the system support Enhanced Intel SpeedStep Technology I...

Page 122: ...hreading Tech Option Values Enabled Disabled Help Text Intel R Hyper Threading Technology allows multithreaded software applications to execute threads in parallel within each processor Contact your OS vendor regarding OS support of this feature Comments This option is only visible if all processors installed in the system support Intel Hyper Threading Technology Back to Advanced Screen Screen Map...

Page 123: ...xecute Disable Bit Option Values Enabled Disabled Help Text Execute Disable Bit can help prevent certain classes of malicious buffer overflow attacks Contact your OS vendor regarding OS support of this feature Comments This option is only visible if all processors installed in the system support the Execute Disable Bit The OS and applications installed must support this feature in order for it to ...

Page 124: ...ption Values Enabled Disabled Help Text Enable Disable Intel R VT d Interrupt Remapping support For some processors this option may be always enabled Comments This option only appears when Intel Virtualization Technology for Directed I O is Enabled For some processors this will be enabled unconditionally whenever Intel VT d is enabled In that case this option will be shown as Enabled and grayed ou...

Page 125: ...setting for Intel TXT will require the system to perform a Hard Reset in order for the new setting to become effective Back to Advanced Screen Screen Map 22 Enhanced Error Containment Mode Option Values Enabled Disabled Help Text Enable Enhanced Error Containment Mode Data Poisoning Erroneous data coming from memory will be poisoned If Disabled default will be in Legacy Mode No data poisoning supp...

Page 126: ... MLC Spatial Prefetcher is normally Enabled for best efficiency in L2 Cache and Memory Channel use but disabling it may improve performance for some processing loads and on certain benchmarks Back to Advanced Screen Screen Map 25 DCU Data Prefetcher Option Values Enabled Disabled Help Text The next cache line will be prefetched into L1 data cache from L2 or system memory during unused cycles if it...

Page 127: ...s Enabled Disabled Help Text When Enabled a SMX can utilize the additional hardware capabilities provided by Safer Mode Extensions Comments Back to Advanced Screen Screen Map 28 SMM Wait Timeout Option Values Entry Field 20 3000ms 20 is default Help Text Millisecond timeout waiting for BSP and APs to enter SMM Range is 20ms to 3000ms Comments Amount of time to allow for the SMI Handler to respond ...

Page 128: ...ect the desired screen Figure 23 Memory Configuration Screen Screen Field Descriptions 1 Total Memory Option Values Total Physical Memory Installed in System Help Text None Comments Information only Displays the amount of memory available in the system in the form of installed DDR3 DIMMs in units of GB Back to Memory Configuration Screen Advanced Screen Screen Map 2 Effective Memory Option Values ...

Page 129: ...ds are 1066 MT s 1333 MT s and 1600 MT s The actual memory speed capability depends on the memory configuration Back to Memory Configuration Screen Advanced Screen Screen Map 4 Memory Operating Speed Selection Option Values Auto 1066 1333 1600 Help Text Force specific Memory Operating Speed or use Auto setting Comments Allows the user to select a specific speed at which memory will operate Only sp...

Page 130: ...memory rank When any one rank accumulates a CE count equal to the CE Threshold then a single CE SEL Event is logged and all further CE logging is suppressed Note that the CE counts are subject to a leaky bucket mechanism that reduces the count as a function of time to keep from accumulating counts unnecessarily over the term of a long operational run Back to Memory Configuration Screen Advanced Sc...

Page 131: ...ge Controller Configuration The Mass Storage Configuration screen allows the user to configure the Mass Storage controllers that are integrated into the server board on which the BIOS is executing This includes only onboard Mass Storage controllers Mass Storage controllers on add in cards are not included in this screen nor are other storage mechanisms such as USB attached storage devices or Netwo...

Page 132: ...d AHCI RAID Mode Help Text Compatibility provides PATA emulation on the SATA device Enhanced provides Native SATA support AHCI enables the Advanced Host Controller Interface which provides Enhanced SATA functionality RAID Mode provides host based RAID support on the onboard SATA ports Comments This option configures the onboard AHCI capable SATA controller The number and type of ports it controls ...

Page 133: ...guration Screen Screen Map 2 AHCI Capable RAID Options Option Values Intel R ESRT2 LSI Intel R RSTe Help Text Intel R ESRT2 Powered by LSI Supports RAID 0 1 10 and optional RAID 5 with Intel RAID C220 Upgrade Keys Uses Intel ESRT2 drivers based on LSI MegaSR Intel R RSTe Provides pass through drive support Also provides host based RAID 0 1 10 5 support Uses Intel R RSTe iastor drivers Comments Thi...

Page 134: ... Storage Controller Configuration Screen Screen Map 4 SATA Port For Port numbers 0 6 Option Values Not Installed Drive Information Help Text None Comments Information only The Drive Information when present will typically consist of the drive model identification and size for the disk drive installed on a particular port This Drive Information line is repeated for all 6 SATA Port for the onboard A...

Page 135: ... Screen Screen Field Descriptions 1 Maximize Memory below 4GB Option Values Enabled Disabled Help Text BIOS maximizes memory usage below 4GB for an OS without PAE support depending on the system configuration Only enable for an OS without PAE support Comments When this option is enabled BIOS makes as much memory available as possible in the 32 bit 4GB address space by limiting the amount of PCI PC...

Page 136: ...Configuration Screen Advanced Screen Screen Map 3 Memory Mapped I O Size Option Values Auto 1G 2G 4G 8G 16G 32G 64G 128G 256G 512G 1024G Help Text Sets MMIO Size Auto 2G default Comments When Memory Mapped I O above 4GB option enabled this option sets the preserved MMIO size as PCI PCIe Memory Mapped I O for devices capable of 64 bit addressing This option is grayed out when Memory Mapped I O abov...

Page 137: ...mments Processor Integrated Graphics is completely disabled if this option is disabled Notes This configuration page is only visible on RM SKU Back to PCI Configuration Screen Advanced Screen Screen Map 6 Primary Display Option Values PCI Add on Card Onboard Video Processor Integrated graphics Help Text Select which of Processor Integrated Graphics Onboard Video PCI Add on Card Graphics device sho...

Page 138: ...Onboard NIC Most boards in this family also can have an IO Module that installs on the board in a specialized connector There are boards which can have two IO Modules installed The descriptive names of the Onboard NIC types are Intel I210 Dual Port Gigabit Ethernet Controller For boards with only one Onboard NIC the Onboard NIC2 entries are not present on the screen The number of Port options whic...

Page 139: ...PXE is enabled then neither iSCSI nor 10 GbE FCoE may be enabled iSCSI there is only one iSCSI Option ROM for both 1 GbE and 10 GbE NICs If iSCSI is enabled then neither PXE nor FCoE OPROMs may be enabled for the 1 GbE or 10 GbE NICs FCoE there is a 10 GbE FCoE Option ROM that supports the Intel 82599 NIC When it is enabled the iSCSI OPROM and the 10 GbE PXE OPROM must be disabled Note These Optio...

Page 140: ...BIOS Setup Interface Intel Server Board S1200V3RP TPS Revision 1 2 126 Figure 26 NIC Configuration Screen Screen Field Descriptions 1 Wake on LAN PME ...

Page 141: ...OM NIC PXE Option ROM Load Comments This selection is to enable disable the 1GbE PXE Option ROM that is used by all Onboard and IO Module 1 GbE controllers This option is grayed out and not accessible if the iSCSI Option ROM is enabled It can co exist with the 10 GbE PXE Option ROM the 10 GbE FCoE Option ROM or with an InfiniBand controller Option ROM If the 1GbE PXE Option ROM is disabled and no ...

Page 142: ...Option Values Enabled Disabled Help Text Enable Disable Onboard IOM NIC FCoE Option ROM Load Comments This selection is to enable disable the 10GbE FCoE Option ROM that is used by all Onboard and IO Module 10 GbE controllers capable of FCoE support At the present time only the Intel 82599 10 Gigabit SFP NIC supports FCoE for this family of server boards This option is grayed out and not accessible...

Page 143: ...Back to NIC Configuration Screen PCI Configuration Screen Advanced Screen Screen Map 6 Onboard NIC1 Type 7 Onboard NIC2 Type Option Values Onboard NIC Description string Intel R I210 Dual Port Gigabit Ethernet Controller Help Text None Comments Information only This is a display showing which NICs are available as Network Controllers integrated into the baseboard Each of these Onboard NICs will be...

Page 144: ... an IO Module is installed and a second IO Module Type and options section will only appear if there are two IO Modules installed Back to NIC Configuration Screen PCI Configuration Screen Advanced Screen Screen Map 10 NIC1 Controller 11 NIC2 Controller Option Values Enabled Disabled Help Text Enable Disable Onboard Network Controller Comments This will completely disable Onboard Network Controller...

Page 145: ... This option only appears for Onboard or IO Module InfiniBand controllers It does not appear for Ethernet controllers Back to NIC Configuration Screen PCI Configuration Screen Advanced Screen Screen Map 15 NIC2 Port1 GUID 16 IOM1 Port1 GUID 17 IOM2 Port1 GUID Option Values GUID Display Help Text None Comments Information only 16 hex digits of the Port1 GUID of the InfiniBand controller for NIC2 IO...

Page 146: ...t state of each Port PXE Boot option is Enabled if the corresponding PXE Boot OPROM of the same speed is Enabled If a PXE Boot OPROM for 1 GbE or 10 GbE changes from Disabled to Enabled then the Port PXE Boot option becomes Enabled for all ports of that speed If the PXE Boot OPROM for1 GbE NICs or 10 GbE NICs is disabled PXE Boot will be disabled and grayed out as unchangeable for all ports on NIC...

Page 147: ...figuration Screen Advanced Screen Screen Map 9 4 2 9 Serial Port Configuration The Serial Port Configuration screen allows the user to configure the Serial A and Serial B ports In Legacy ISA nomenclature these are ports COM1 and COM2 respectively To access this screen from the Main screen select Advanced Serial Port Configuration To move to another screen press the Esc key to return to the Advance...

Page 148: ...3F8h 2F8h 3E8h 2E8h Help Text Select Serial port A base I O address Comments Legacy I O port address This field should not appear when Serial A port enable disable does not appear Back to Serial Port Configuration Screen Screen Map 3 IRQ Option Values 3 4 Help Text Select Serial port A interrupt request IRQ line Comments Legacy IRQ This field should not appear when Serial A port enable disable doe...

Page 149: ...al port B interrupt request IRQ line Comments Legacy IRQ Back to Serial Port Configuration Screen Screen Map 9 4 2 10 USB Configuration The USB Configuration screen allows the user to configure the available USB controller options To access this screen from the Main screen select Advanced USB Configuration To move to another screen press the Esc key to return to the Advanced screen then select the...

Page 150: ...tition Table will be forced to FDD emulation A USB Key formatted with one Partition Table and less than 528 MB in size will be forced to FDD emulation otherwise if it is 528 MB or greater in size it will be forced to HDD emulation Note USB devices can be hotplugged during POST and will be detected and beeped They will be enumerated and displayed on this screen though they may not be enumerated as ...

Page 151: ... inaccessible by the OS Comments When the USB controllers are Disabled there is no USB IO available for either POST or the OS In that case all following fields on this screen are grayed out and inactive Back to USB Configuration Screen Screen Map 3 Legacy USB Support Option Values Enabled Disabled Auto Help Text Enables Legacy USB support AUTO option disables legacy support if no USB devices are c...

Page 152: ...hip change should be claimed by XHCI driver Comments If the USB controller setting is Disabled this field is grayed out and inactive Back to USB Configuration Screen Screen Map 6 EHCI Hand off Option Values Enabled Disabled Help Text This is a workaround for OSes without EHCI hand off support The XHCI ownership change should be claimed by EHCI driver Comments If the USB controller setting is Disab...

Page 153: ...s Storage devices as Boot options Comments This is a security option When Disabled the system cannot be booted directly to a USB device of any kind USB Mass Storage devices may still be used for data storage If the USB controller setting is Disabled this field is grayed out and inactive Back to USB Configuration Screen Screen Map 9 Device Reset Timeout Option Values 10 seconds 20 seconds 30 second...

Page 154: ...count but only the first eight devices discovered are displayed in this list If the USB controller setting is Disabled this field is grayed out and inactive Back to USB Configuration Screen Screen Map 9 4 2 11 System Acoustic and Performance Configuration The System Acoustic and Performance Configuration screen allows the user to configure the thermal control behavior of the system with respect to...

Page 155: ...hermal data are available Note that this is for thermal throttling only independent of any controls imposed for the purpose of power limiting CLTM would be used with an OEM chassis and DIMMs with TSOD The firmware does not change the offset registers for closed loop during runtime although the Management Engine can do so OLTM is intended for a system with UDIMMs which do not have TSOD The thermal ...

Page 156: ...ions in the system are controlled by raising fan speed when necessary to raise cooling performance This provides cooling without impacting system performance but may impact system acoustic performance fans running faster are typically louder When Acoustic is selected then rather than increasing fan speed for additional cooling the system will attempt first to control thermal conditions by throttli...

Page 157: ...un as needed to maintain thermal control The actual decrease in fan speed depends on the system thermal loading which in turn depends on system configuration and workload While Quiet Fan Idle Mode is engaged fan sensors become unavailable and are not monitored by the BMC Quiet Fan Idle Mode does not conflict with Fan PWM Offset above they work in concert with Fan PWM Offset applied to fans in Quie...

Page 158: ...lows the user to enable and activate the Trusted Platform Module TPM security settings on those boards that support TPM Note that it is necessary to activate the TPM in order be able to enable Intel Trusted Execution Technology TXT on boards that support it Changing the TPM state in Setup will require a Hard Reset for the new state to become effective This BIOS supports but does not require Strong...

Page 159: ...er top level Tab screen press the right or left arrow keys to traverse the tabs at the top of the Setup screen until the Security screen is selected Figure 31 Security Screen Screen Field Descriptions 1 Administrator Password Status Option Values Installed Not Installed Help Text None Comments Information only Indicates the status of the Administrator Password Back to Security Screen Screen Map 2 ...

Page 160: ...stem Deleting all characters in the password entry field removes a password previously set Clearing the Administrator Password also clears the User Password If invalid characters are present in the password entered it will not be accepted and there will be popup error message Password entered is not valid Only case sensitive alphabetic numeric and special characters _ are allowed The Administrator...

Page 161: ...ror and warning message are the same for the User password as for the Administrator password see above Back to Security Screen Screen Map 5 Power On Password Option Values Enabled Disabled Help Text Enable Power On Password support If enabled password entry is required in order to boot the system Comments When Power On Password security is enabled the system will halt soon after power on and the B...

Page 162: ...ows the current TPM device state A Disabled TPM device does not execute commands that use the TPM functions and TPM security operations are not available An Enabled Deactivated TPM is in the same state as a disabled TPM except that setting of the TPM ownership is allowed if it is not present already An Enabled Activated TPM executes all commands that use the TPM functions and TPM security operatio...

Page 163: ...ve Note This option appears only on boards equipped with a TPM Back to Security Screen Screen Map 9 4 2 14 Server Management Screen Tab The Server Management screen allows the user to configure several server management features This screen also provides an access point to the screens for configuring Console Redirection displaying system information and controlling the BMC LAN configuration To acc...

Page 164: ...ERR Option Values Enabled Disabled Help Text On SERR generate an NMI and log an error Note Enabled must be selected for the Assert NMI on PERR setup option to be visible Comments This option allows the system to generate an NMI when an SERR occurs which is a method Legacy Operating System error handlers may use instead of processing a Machine Check ...

Page 165: ...n CATERR Option Values Enabled Disabled Help Text When enabled system gets reset upon encountering Catastrophic Error CATERR when disabled system does not get reset on CATERR Comments This option controls whether the system will be reset when the Catastrophic Error CATERR signal is held asserted rather than just pulsed to generate an SMI This indicates that the processor has encountered a fatal ha...

Page 166: ...en Screen Map 5 Power Restore Delay Option Values Disabled Auto Fixed Help Text Allows a delay in powering up after a power failure to reduce peak power requirements The delay can be fixed or automatic between 25 300 seconds Comments When the AC power resume policy above is either Power On or Last State this option allows a delay to be taken after AC power is restored before the system actually be...

Page 167: ... Restore Delay selection is Fixed this field allows for specifying how long in seconds that fixed delay will be When the Power Restore Delay is Disabled or Auto this field will be grayed out and unavailable The Power Restore Delay Value setting is maintained by BIOS This setting does not take effect until a reboot is done Early in POST the Power Restore Policy is read from the BMC and if the polic...

Page 168: ...ack to Server Management Screen Screen Map 9 OS Boot Watchdog Timer Option Values Enabled Disabled Help Text BIOS programs the watchdog timer with the timeout value selected If the OS does not complete booting before the timer expires the BMC will reset the system and an error will be logged Requires OS support or Intel Management Software Support Comments This option controls whether the system w...

Page 169: ...eset System performs a reset Power Off System powers off Comments This option is grayed out and unavailable when the O S Boot Watchdog Timer is disabled Back to Server Management Screen Screen Map 11 OS Boot Watchdog Timer Timeout Option Values 5 minutes 10 minutes 15 minutes 20 minutes Help Text If the OS watchdog timer is enabled this is the timeout value BIOS will use to configure the watchdog ...

Page 170: ...codesign EuP LOT6 Deep Sleep Off Mode for near zero energy use when powered off Comments This option controls whether the system goes into Deep Sleep or more conventional S5 Soft Off when powered off Deep Sleep state uses less energy than S5 but S5 can start up faster and can allow a Wake on LAN action which cannot be done from a Deep Sleep state This option will not appear on platforms which do n...

Page 171: ...onnection options for this feature To access this screen from the Main screen select Server Management Console Redirection To move to another screen press the Esc key to return to the Server Management screen then select the desired screen When Console Redirection is active all POST and Setup displays are in Text Mode The Quiet Boot setting is disregarded and the Text Mode POST Diagnostic Screen w...

Page 172: ...edirection is set to Disabled all other options on this screen will be grayed out and unavailable Only Serial Ports which are Enabled should be available to choose for Console Redirection If neither Serial A nor Serial B is set to Enabled then Console Redirection will be forced to Disabled and grayed out as inactive In that case all other options on this screen will also be grayed Back to Console ...

Page 173: ...most modern Server Management applications serial data transfer is consolidated over an alternative faster medium like LAN and 115 2k is the speed of choice When Console Redirection is set to Disabled this option will be grayed out and unavailable Back to Console Redirection Screen Server Management Screen Screen Map 4 Terminal Type Option Values PC ANSI VT100 VT100 VT UTF8 Help Text Character for...

Page 174: ...sabled this option will be grayed out and unavailable Back to Console Redirection Screen Server Management Screen Screen Map 6 Terminal Resolution Option Values 80x24 100x31 Help Text Remote Terminal Resolution Comments This option allows the use of a larger terminal screen area although it does not change Setup displays to match When Console Redirection is set to Disabled this option will be gray...

Page 175: ...isplay Help Text None Comments Information only Back to System Information Screen Server Management Screen Screen Map 2 Board Serial Number Option Values Serial Number display Help Text None Comments Information only Back to System Information Screen Server Management Screen Screen Map 3 System Part Number Option Values Part Number display Help Text None Comments Information only ...

Page 176: ...ments Information only Back to System Information Screen Server Management Screen Screen Map 6 Chassis Serial Number Option Values Serial Number display Help Text None Comments Information only Back to System Information Screen Server Management Screen Screen Map 7 Asset Tag Option Values Asset Tag display Help Text None Comments Information only Back to System Information Screen Server Management...

Page 177: ...n select the desired screen The BMC configuration screen allows the user to configure the BMC Baseboard LAN channel and an Intel RMM4 LAN channel and to manage BMC User settings for up to five BMC Users An Intel RMM4 Management Module may be installed in the server system If the Management Module is installed it may also have a Dedicated Server Management NIC Module DMN installed with it In that c...

Page 178: ...ch does not require a DHCP server The BMC LAN Configuration screen is unusual in that the LAN Configuration parameters are maintained by the BMC itself so this screen is just a User Interface to the BMC configuration As such the initial values of the LAN options shown on the screen are acquired from the BMC when this screen is initially accessed by a user Any values changed by the user are communi...

Page 179: ...Intel Server Board S1200V3RP TPS BIOS Setup Interface Revision 1 2 165 Figure 35 BMC LAN Configuration Screen Screen Field Descriptions 1 IP Source Option Values Static Dynamic Help Text ...

Page 180: ...Help Text View Edit IP Address Press Enter to edit Comments This specifies the IPv4 Address for the Baseboard LAN There is a separate IPv4 Address field for the Intel RMM4 LAN configuration When IPv4 addressing is used the initial value for this field is acquired from the BMC The setting of IP Source determines whether this field is display only when Dynamic or can be edited when Static When IPv6 ...

Page 181: ...can be edited when Static When IPv6 addressing is enabled this field is grayed out and inactive Back to BMC LAN Configuration Screen Server Management Screen Screen Map 5 IPv6 Option Values Enabled Disabled Help Text Option to Enable Disable IPv6 addressing and any IPv6 network traffic on these channels Comments The initial value for this field is acquired from the BMC It may be changed in order t...

Page 182: ...r can be edited when Static Back to BMC LAN Configuration Screen Server Management Screen Screen Map 7 IPv6 Address Option Values Entry Field 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 is default Help Text View Edit IPv6 address Press Enter to edit IPv6 addresses consist of 8 hexadecimal 4 digit numbers separated by colons Comments This specifies the IPv6 Addre...

Page 183: ...Length from zero to 128 default 64 Press Enter to edit Comments This specifies the IPv6 Prefix Length for the Baseboard LAN There is a separate IPv6 Prefix Length field for the Intel RMM4 LAN configuration This option is only visible when the IPv6 option is set to Enabled When IPv6 addressing is used the initial value for this field is acquired from the BMC The setting of IPv6 Source determines wh...

Page 184: ...fies the IP Source for IPv4 addressing for the Intel RMM4 DMN LAN connection There is a separate IP Source field for the Baseboard LAN configuration When IPv4 addressing is used the initial value for this field is acquired from the BMC and its setting determines whether the other Intel RMM4 DMN LAN IPv4 addressing fields are display only when Dynamic or can be edited when Static When IPv6 addressi...

Page 185: ... Static When IPv6 addressing is enabled this field is grayed out and inactive Back to BMC LAN Configuration Screen Server Management Screen Screen Map 14 Gateway IP Option Values Entry Field 0 0 0 0 0 0 0 0 is default Help Text View Edit Gateway IP Press Enter to edit Comments This specifies the IPv4 addressing Gateway IP for the Intel RMM4 DMN LAN There is a separate IPv4 Gateway IP field for the...

Page 186: ...to or can be edited when Static Back to BMC LAN Configuration Screen Server Management Screen Screen Map 16 IPv6 Address Option Values Entry Field 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 is default Help Text View Edit IPv6 address Press Enter to edit IPv6 addresses consist of 8 hexadecimal 4 digit numbers separated by colons Comments This specifies the IPv6 ...

Page 187: ... for the Intel RMM4 DMN LAN There is a separate IPv6 Prefix Length field for the Baseboard LAN configuration This option is only visible when the IPv6 option is set to Enabled When IPv6 addressing is used the initial value for this field is acquired from the BMC The setting of IPv6 Source determines whether this field is display only when Dynamic or Auto or can be edited when Static Back to BMC LA...

Page 188: ... are supported Comments These 5 User IDs are fixed choices and cannot be changed The BMC supports 15 User IDs natively but only the first 5 are supported through this interface Back to BMC LAN Configuration Screen Server Management Screen Screen Map 21 Privilege Option Values Callback User Operator Administrator Help Text View Select user privilege User2 root privilege is Administrator and cannot ...

Page 189: ... Comments User Name can only be edited for users other than anonymous and root Those two User Names may not be changed Back to BMC LAN Configuration Screen Server Management Screen Screen Map 24 User Password Option Values Popup Entry Field 0 15 characters Help Text Press Enter key to enter password Maximum length is 15 characters Any ASCII printable characters can be used case sensitive alphabeti...

Page 190: ...ootable devices they will appear as Boot Devices if appropriate If they were recognized after Boot Device enumeration they will not appear as a bootable device for the Boot Options screen the Boot Manager screen or the F6 Boot Menu There are two main types of boot order control Legacy Boot and EFI Optimized boot These are mutually exclusive when EFI Optimized Boot is enabled Legacy Boot the defaul...

Page 191: ... the end of POST to allow the user to press the F2 key for entering the BIOS Setup utility Valid values are 0 65535 Zero is the default A value of 65535 causes the system to go to the Boot Manager menu and wait for user input for every system boot Comments After entering the desired timeout press the Enter key to register that timeout value to the system These settings are in seconds The timeout v...

Page 192: ...boot from the first device on the list which is available and bootable This establishes the Boot Order only with respect to the normal boot path This order has no effect on the Boot Manager selection list or the F6 BIOS Boot Menu popup both of which simply list all bootable devices available in the order in which they were detected Whether or not a potential Boot Device is in this list has no bear...

Page 193: ...f the legacy devices in this group Comments Selection only Select this line and press the Enter key to go to the Floppy Order Screen This option appears when one or more bootable Floppy Disk drives are available in the system This includes USB Floppy Disk devices and USB Keys formatted for Floppy Disk emulation Back to Boot Options Screen Back to Screen Map 8 Network Device Order Option Values Non...

Page 194: ...t this line and press the Enter key to go to the Add EFI Boot Option Screen This option is only displayed if an EFI bootable device is available to the system Back to Boot Options Screen Back to Screen Map 11 Delete EFI Boot Option Option Values None Help Text Remove an EFI boot option from the boot order Comments Selection only Select this line and press the Enter key to go to the Delete EFI Boot...

Page 195: ...Enabled Disabled Help Text If enabled this continually retries non EFI based boot options without waiting for user input Comments This option is intended to keep retrying for cases where the boot devices could possibly be slow to initially respond e g if the device were asleep and did not wake quickly enough However if none of the devices in the Boot Order ever responds the BIOS will continue to r...

Page 196: ...om Disabled it will enable Static Boot Order SBO from the next boot onward and also the current Boot Order will be stored as the SBO template When the option changes from Enabled to Disabled this will disable SBO and the SBO template will be cleared Otherwise it will retain the current Enabled Disabled state Back to Boot Options Screen Back to Screen Map 17 Reset Static Boot Order Option Values Ye...

Page 197: ...other screen press the Esc key to return to the Boot Options screen then select the desired screen Figure 37 CDROM Order Screen Screen Field Descriptions 1 CDROM 1 2 CDROM 2 Option Values Available CDROM devices Help Text Set system boot order by selecting the boot option for this position Comments Choose the order of booting among CDROM devices by choosing which available CDROM device should be i...

Page 198: ...hoosing which available Hard Disk device should be in each position in the order Back to Hard Disk Order Screen Boot Options Screen Screen Map 9 4 2 21 Floppy Order The Floppy Order screen allows the user to control the order in which BIOS attempts to boot from the Floppy Disk drives installed in the system This screen is only available when there is at least one Floppy Disk diskette device availa...

Page 199: ...der Back to Floppy Order Screen Boot Options Screen Screen Map 9 4 2 22 Network Device Order The Network Device Order screen allows the user to control the order in which BIOS attempts to boot from the network bootable devices installed in the system This screen is only available when there is at least one network bootable device available in the system configuration To access this screen from the...

Page 200: ...to boot from the BEV Devices installed in the system This screen is only available when there is at least one BEV device available in the system configuration To access this screen from the Main screen select Boot Options BEV Device Order To move to another screen press the Esc key to return to the Boot Options screen then select the desired screen Figure 41 BEV Device Order Screen Screen Field De...

Page 201: ...ion To move to another screen press the Esc key to return to the Boot Options screen then select the desired screen Figure 42 Add EFI Boot Option Screen Screen Field Descriptions 1 Add boot option label Option Values Enter label Help Text Create the label for the new boot option Comments This label becomes an abbreviation for this Boot Path Back to Add EFI Boot Option Screen Boot Options Screen Sc...

Page 202: ...he new Boot Option into the Boot Order Back to Add EFI Boot Option Screen Boot Options Screen Screen Map 9 4 2 25 Delete EFI Boot Option The Delete EFI Boot Option screen allows the user to remove an EFI boot option from the boot order The Internal EFI Shell Boot Option will not be listed since it is permanent and cannot be added or deleted To access this screen from the Main screen select Boot Op...

Page 203: ...ell will always be available Note This list is not in order according to the system Boot Option order Reordering Boot Devices or even removing them from the Boot Order completely has no effect on the Boot Manager To access this screen from the Main screen or other top level Tab screen press the right or left arrow keys to traverse the tabs at the top of the Setup screen until the Boot Manager scre...

Page 204: ...re not displayed in any specified order particularly not in the system Boot Order established by the Boot Options screen This is just a list of bootable devices in the order in which they were enumerated Back to Boot Manager Screen Screen Map 9 4 2 27 Error Manager Screen Tab The Error Manager screen displays any POST Error Codes encountered during BIOS POST along with an explanation of the meanin...

Page 205: ...POST Error Code that is being reported Back to Error Manager Screen Screen Map 4 DESCRIPTION Option Values N A Help Text Description of POST Error Code Comments This is a description of the meaning of the POST Error Code that is being reported This text actually appears in the screen space that is usually reserved for Help messages Back to Error Manager Screen Screen Map 9 4 2 28 Save Exit Screen ...

Page 206: ...ain brands and names may be claimed as the property of others This is reference to any instance in the Setup screens where names belonging to other companies may appear For example LSI appears in Setup in the context of Mass Storage RAID options Figure 46 Save Exit Screen Screen Field Descriptions 1 Save Changes and Exit Option Values None Help Text Exit BIOS Setup Utility after saving changes The...

Page 207: ...there have been no changes made in the settings the BIOS will resume executing POST If changes have been made in BIOS settings a confirmation pop up will appear If the Discard Changes Exit action is positively confirmed all pending changes will be discarded and BIOS will resume executing POST If the Discard Changes Exit action is not confirmed BIOS will resume executing Setup without discarding an...

Page 208: ...oad Default Values Option Values None Help Text Load Defaults Values for all the setup options Comments Selection only Select this line and press the Enter key to load default values for all BIOS settings These are the initial factory settings failsafe settings for all BIOS parameters There will be a confirmation popup to verify that the user really meant to take this action After initializing all...

Page 209: ...es they were saved as Back to Save Exit Screen Screen Map 7 Load User Default Values Option Values None Help Text Load the User Default Values to all the setup options Comments Selection only Select this line and press the Enter key to load User Default Values for all BIOS settings These are user customized BIOS default settings for all BIOS parameters previously established by doing a Save User D...

Page 210: ...abled in the Server Management tab in Setup see Figure 32 and drivers must be installed Refer to the IFlash32 program Release Notes for information on this The following procedure shows the steps necessary to update the BIOS using IFlash32 running under the UEFI Shell The assumption is that the user has obtained a BIOS release in compressed Zip format typically by downloading it from the Intel Sup...

Page 211: ... power loss during the IFlash32 BIOS Update Try rebooting to the EFI Shell If that is successful restart the BIOS Update If the boot to the EFI Shell fails perform a Recovery Boot see Section 9 6 using the Recovery capsule from the previously installed BIOS that is the BIOS version before the update Refer to the BIOS Release Notes and the IFlash32 program Release Notes for the most complete and ac...

Page 212: ...t the external medium with the capsule file and IFlash32 to it 4 Go to the directory where iflash32 efi is present on the external medium 5 Run the command iflash32 u ni CapsuleFileName cap UpdateBackupBios where u update the System BIOS ni update will be in non interactive mode CapsuleFileName cap replace with name of BIOS capsule file UpdateBackupBios update the system backup BIOS 6 It will upda...

Page 213: ...ating that the BIOS has been updated successfully indicating the recovery process is finished The User should then switch the recovery jumper back to normal operation and restart the system by performing a power cycle Step by step this process goes as follows 1 Power off the system Removing AC power is not necessary but may be advisable due to safety considerations or if a riser or other hardware ...

Page 214: ...ware moved and close the chassis 10 Remove Recovery medium 11 Replug AC cords if removed and power on the system 12 Do NOT interrupt the BIOS POST during the first boot 13 Boot the system into Setup The Recovery Boot process will reset BIOS settings to default values 14 Go to the Setup Main tab see Figure 20 and set the System Date and System Time to the correct current settings Make any other cha...

Page 215: ...entify the location of each jumper block and provides a description of their use The following symbol identifies Pin 1 on each jumper block on the silkscreen Figure 47 Jumper Blocks J2K6 J2K8 J2K9 J3K2 J3K6 Note 1 For safety purposes the power cord should be disconnected from a system before removing any system components or moving any of the on board jumper blocks 2 System Update and Recovery fil...

Page 216: ...nabled J3K6 BMC Force Update 1 2 BMC Firmware Force Update Mode Disabled Default 2 3 BMC Firmware Force Update Mode Enabled 10 1 BIOS Default Jumper Block 1 This jumper resets BIOS Setup options to their default factory settings 2 Power down the server and unplug the power cords 3 Open the chassis and remove the Riser 2 assembly 4 Move BIOS DFLT jumper from the default pins 1 and 2 position to the...

Page 217: ...NOT interrupt the BIOS POST during the first boot 11 Configure desired BIOS settings 10 3 Password Clear Jumper Block This jumper causes both the User password and the Administrator password to be cleared if they were set The operator should be aware that this creates a security gap until passwords have been installed again through the BIOS Setup utility This is the only method by which the Admini...

Page 218: ...uld be followed Note System Update and Recovery files are included in the System Update Packages SUP posted to Intel s website 1 Turn off the system and remove power cords 2 Remove Riser Card Assembly 2 3 Move the ME FRC UPD Jumper from the default pins 1 and 2 operating position to the Force Update position pins 2 and 3 4 Re attach system power cords 5 Power on the system Note System Fans will bo...

Page 219: ...ion to the Force Update position pins 2 and 3 3 Re attach system power cords 4 Power on the system Note System Fans will boost and the BIOS Error Manager should report an 84F3 error code Baseboard Management Controller in update mode 5 Boot to the EFI shell and update the BMC firmware using BMC NSH where is the version number of the BMC 6 When update has successfully completed power off system 7 R...

Page 220: ...1200V3RP TPS Revision 1 2 206 11 Intel Light Guided Diagnostics The server board includes several on board LED indicators to aid troubleshooting various board level faults The following figure shows the location for each Figure 48 On Board LED Placement ...

Page 221: ...nd then immediately changes to blinking green to indicate that the BMC is booting If the BMC boot process completes with no errors the status LED will change to solid green Table 59 System Status LED State Definitions Color State Criticality Description Off System is not operating Not ready 1 System is powered off AC and or DC 2 System is in EuP Lot6 Off Mode 3 System is in S5 Soft Off State 4 Sys...

Page 222: ...graded Amber 1 Hz blink Non critical System is operating in a degraded state with an impending failure warning although still functioning Non fatal alarm system is likely to fail Critical threshold crossed Voltage temperature including HSBP temp input power to power supply output current for main power rail from power supply and PROCHOT Therm Ctrl sensors VRD Hot asserted Minimum number of fans to...

Page 223: ... on replacing this motherboard BMC in u Boot Blink Blue 3Hz Blink Green 1Hz Blinking green indicates degraded state no manageability blinking blue indicates u Boot is running but has not transferred control to BMC Linux Server will be in this state 6 8 seconds after BMC reset while it pulls the Linux image into flash BMC Booting Linux Solid Blue Solid Green Solid green with solid blue after an AC ...

Page 224: ... 5 Volt Stand By Present LED This LED is illuminated when a power cord AC or DC is connected to the server and the power supply is supplying 5 Volt Stand by power to the server board This LED is intended as a service caution indicator to anyone accessing the inside of the server system ...

Page 225: ...ow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of its published operating or non operating limits Disclaimer Note Intel ensures the unpackaged server board and system meet the shock requirement mentioned above through its own chassis developm...

Page 226: ... The following is the calculated Mean Time Between Failures MTBF 40 degree C ambient air These values are derived using a historical failure rate and multiplied by factors for application electrical and or thermal stress and for device maturity You should view MTBF estimates as reference numbers only Calculate standard Telcordia issue 2 Calculate Method Method I D Temperature 40 degree C Environme...

Page 227: ...in an Intel designed 4U server platform The intent of this section is to provide customers with a guide to assist in defining and or selecting a power supply for custom server platform designs that utilize the server boards detailed in this document Figure 49 Power Distribution Block Diagram 13 1 DC Output Specification 13 1 1 Output Power Currents The following table defines the minimum power and...

Page 228: ... 8 2 16 10 5 0 0 3 365 318 46 Load2 18 4 1 7 6 16 0 0 3 365 283 80 Load3 18 4 1 16 7 6 0 0 3 365 283 80 Load4 13 6 7 10 2 12 0 5 2 5 365 266 80 Load5 0 5 0 3 0 7 1 5 0 0 3 31 26 3 Load6 16 4 0 7 2 6 0 0 3 114 40 73 Load7 1 2 2 7 14 5 7 1 0 1 282 259 17 13 1 3 Standby Output The 5VSB output is present when an AC input greater than the power supply turn on voltage is applied 13 1 4 Voltage Regulatio...

Page 229: ... the following capacitive loading ranges Table 67 Capacitive Loading Conditions Output MIN MAX Units 3 3V 250 5000 F 5V 400 5000 F 12V 500 8000 F 12V 1 350 F 5VSB 20 350 F 13 1 7 Grounding The output ground of the pins of the power supply provides the output power return path The output connector ground pins are connected to the safety ground power supply enclosure This grounding is well designed ...

Page 230: ...p p 120mVp p 120mVp p 200mVp p 50mVp p The test set up shall be as shown below AC HOT POWER SUPPLY AC NEUTRAL V OUT RETURN V AC GROUND LOAD SCOPE LOAD MUST BE ISOLATED FROM THE GROUND OF THE POWER SUPPLY 10uF 1uF GENERAL NOTES 1 LOAD THE OUTPUT WITH ITS MINIMUM LOAD CURRENT 2 CONNECT THE PROBES AS SHOWN 3 REPEAT THE MEASUREMENTS WITH THE MAXIMUM LOAD ON THE OUTPUT SCOPE NOTE USE A TEKTRONIX 7834 O...

Page 231: ...ach other within this time 50 ms Tvout_off All main outputs must leave regulation within this time 400 ms Figure 51 Output Voltage Timing Table 70 Turn On Off Timing Item Description Min Max Units Tsb_on_delay Delay from AC being applied to 5VSB being within regulation 1500 ms T ac_on_delay Delay from AC being applied to all output voltages being within regulation 2500 ms Tvout_holdup Time all out...

Page 232: ... 1 ms Tpwok_low Duration of PWOK being in the de asserted state during an off on cycle using AC or the PSON signal 100 ms Tsb_vout Delay from 5VSB being in regulation to O Ps being in regulation at AC turn on 10 1000 ms T5VSB_holdup Time the 5VSB output voltage stays within regulation after loss of AC 70 ms AC Input Vout PWOK 5VSB PSON Tsb_on_delay TAC_on_delay Tpwok_on Tvout_holdup Tpwok_holdup T...

Page 233: ... UDIMMs are supported on this server board Mixing of RDIMMs and UDIMMs is not supported The Intel RMM4 RMM4 Lite connectors are not compatible with the previous Intel Remote Management Modules Clear CMOS with the AC power cord plugged in Removing AC power before performing the CMOS Clear operation causes the system to automatically power up and immediately power down after the CMOS Clear procedure...

Page 234: ...itical uc lc upper critical lower critical Event Triggers are supported event generating offsets for discrete type sensors You can find the offsets in the Generic Event Reading Type Codes or Sensor Type Codes tables in the IPMI specification depending on whether the sensor event reading type is generic or a sensor specific response Assertion De assertion Enables Assertion and de assertion indicato...

Page 235: ...set Triggers Contrib To System Status Assert De assert Reada ble Value Offset s Event Data Rearm St an db y Power Unit Status Pwr Unit Status 01 h All Power Unit 09h Sensor Specifi c 6Fh 00 Power down OK As and De Trig Offset A X 02 240 VA power down Fatal 04 A C lost OK 05 Soft power control failure Fatal 06 Power unit failure Power Unit Redundancy 1 Pwr Unit Redund 02 h Chassis specific Power Un...

Page 236: ...06 h All SMI Timeou t F3h Digital Discret e 03h 01 State asserted Fatal As and De Trig Offset A System Event Log System Event Log 07 h All Event Loggin g Disable d 10h Sensor Specifi c 6Fh 02 Log area reset cleared OK As Trig Offset A X System Event System Event 08 h All System Event 12h Sensor Specifi c 6Fh 02 Undetermined system H W failure Fatal As and De As Trig Offset A X 04 PEF action OK But...

Page 237: ...latform specific Module Board 15h Digital Discret e 08h 01 Inserted Present OK As and De Trig Offset M SAS Module Presence SAS Mod Presence 0 F h Platform specific Module Board 15h Digital Discret e 08h 01 Inserted Present OK As and De Trig Offset M X BMC Firmware Health BMC FW Health 10 h All Mgmt Health 28h Sensor Specifi c 6Fh 04 Sensor Failure Degrad ed As Trig Offset A X System Airflow System...

Page 238: ...orm specific Temper ature 01h Thresh old 01h u l c nc nc Degrad ed c Non fatal As and De Analo g R T A X PCI Riser 4 Temperature PCI Riser 4 Temp 18 h Platform specific Temper ature 01h Thresh old 01h u l c nc nc Degrad ed c Non fatal As and De Analo g R T A X Baseboard 1 05V Processor3 Vccp BB 1 05Vccp P3 19 h Platform specific Voltage 02h Thresh old 01h u l c nc nc Degrad ed c Non fatal As and D...

Page 239: ...on fatal As and De Analo g R T A X Baseboard Temperature 4 Platform Specific 25 h Platform specific Temper ature 01h Thresh old 01h u l c nc nc Degrad ed c Non fatal As and De Analo g R T A X IO Module Temperature I O Mod Temp 26 h Platform specific Temper ature 01h Thresh old 01h u l c nc nc Degrad ed c Non fatal As and De Analo g R T A X PCI Riser 1 Temperature PCI Riser 1 Temp 27 h Platform spe...

Page 240: ...form specific Temper ature 01h Thresh old 01h u l c nc nc Degrad ed c Non fatal As and De Analo g R T A X Exit Air Temperature Exit Air Temp 2 E h Chassis and Platform Specific Temper ature 01h Thresh old 01h u l c nc nc Degrad ed c Non fatal As and De Analo g R T A X Network Interface Controller Temperature LAN NIC Temp 2 F h All Temper ature 01h Thresh old 01h u l c nc nc Degrad ed c Non fatal A...

Page 241: ... Input PS1 Power In 54 h Chassis specific Other Units 0Bh Thresh old 01h u c nc nc Degrad ed c Non fatal As and De Analo g R T A X Power Supply 2 AC Power Input PS2 Power In 55 h Chassis specific Other Units 0Bh Thresh old 01h u c nc nc Degrad ed c Non fatal As and De Analo g R T A X Power Supply 1 12V of Maximum Current Output PS1 Curr Out 58 h Chassis specific Current 03h Thresh old 01h u c nc n...

Page 242: ...70 h All Proces sor 07h Sensor Specifi c 6Fh 01 Thermal trip Fatal As and De Trig Offset M X 07 Presence OK Processor 2 Status P2 Status 71 h All Proces sor 07h Sensor Specifi c 6Fh 01 Thermal trip Fatal As and De Trig Offset M X 07 Presence OK Processor 3 Status P3 Status 72 h Platform specific Proces sor 07h Sensor Specifi c 6Fh 01 Thermal trip Fatal As and De Trig Offset M X 07 Presence OK Proc...

Page 243: ...d 01h u c nc nc Degrad ed c Non fatal As and De Analo g Trig Offset A Processor 4 Thermal Control P4 Therm Ctrl 7 B h Platform specific Temper ature 01h Thresh old 01h u c nc nc Degrad ed c Non fatal As and De Analo g Trig Offset A Processor 1 ERR2 Timeout P1 ERR2 7 C h All Proces sor 07h Digital Discret e 03h 01 State Asserted fatal As and De Trig Offset A Processor 2 ERR2 Timeout P2 ERR2 7 D h A...

Page 244: ...alo g R T A Processor 2 DTS Thermal Margin P2 DTS Therm Mgn 84 h All Temper ature 01h Thresh old 01h Analo g R T A Processor 3 DTS Thermal Margin P3 DTS Therm Mgn 85 h All Temper ature 01h Thresh old 01h Analo g R T A Processor 4 DTS Thermal Margin P4 DTS Therm Mgn 86 h All Temper ature 01h Thresh old 01h Analo g R T A Processor2 MSID Mismatch P2 MSID Mismatch 87 h All Proces sor 07h Digital Discr...

Page 245: ... e 05h 01 Limit exceeded Non fatal As and De Trig Offset A Processor 2 Memory VRD Hot 0 1 P2 Mem01 VRD Hot 96 h All Temper ature 01h Digital Discret e 05h 01 Limit exceeded Non fatal As and De Trig Offset A Processor 2 Memory VRD Hot 2 3 P2 Mem23 VRD Hot 97 h All Temper ature 01h Digital Discret e 05h 01 Limit exceeded Non fatal As and De Trig Offset A Processor 3 Memory VRD Hot 0 1 P3 Mem01 VRD H...

Page 246: ...ig Offset M Power Supply 2 Fan Tachometer 1 PS2 Fan Tach 1 A 4h Chassis specific Fan 04h Generi c digital discret e 01 State Asserted Non fatal As and De Trig Offset M Power Supply 2 Fan Tachometer 2 PS2 Fan Tach 2 A 5h Chassis specific Fan 04h Generi c digital discret e 01 State Asserted Non fatal As and De Trig Offset M Processor 1 DIMM Aggregate Thermal Margin 1 P1 DIMM Thrm Mrgn1 B 0h All Temp...

Page 247: ...T A Processor 3 DIMM Aggregate Thermal Margin 2 P3 DIMM Thrm Mrgn2 B 5h Platform Specific Temper ature 01h Thresh old 01h u l c nc nc Degrad ed c Non fatal As and De Analo g R T A Processor 4 DIMM Aggregate Thermal Margin 1 P4 DIMM Thrm Mrgn1 B 6h Platform Specific Temper ature 01h Thresh old 01h u l c nc nc Degrad ed c Non fatal As and De Analo g R T A Processor 4 DIMM Aggregate Thermal Margin 2 ...

Page 248: ...al Trip P4 Mem Thrm Trip C 3h All Memor y 0Ch Digital Discret e 03h 0A Critical overtemperature Fatal As and De Trig Offset M X Global Aggregate Temperature Margin 1 Agg Therm Mrgn 1 C 8h Platform Specific Temper ature 01h Thresh old 01h Analo g R T A Global Aggregate Temperature Margin 2 Agg Therm Mrgn 2 C 9h Platform Specific Temper ature 01h Thresh old 01h Analo g R T A Global Aggregate Tempera...

Page 249: ...Thresh old 01h Analo g R T A Baseboard 12V BB 12 0V D 0h All Voltage 02h Thresh old 01h u l c nc nc Degrad ed c Non fatal As and De Analo g R T A Baseboard 5V BB 5 0V D 1h All Voltage 02h Thresh old 01h u l c nc nc Degrad ed c Non fatal As and De Analo g R T A Baseboard 3 3V BB 3 3V D 2h All Voltage 02h Thresh old 01h u l c nc nc Degrad ed c Non fatal As and De Analo g R T A Baseboard 5V Stand by ...

Page 250: ...aseboard 1 5V P1 Memory CD VDDQ BB 1 5 P1MEM CD D 9h All Voltage 02h Thresh old 01h u l c nc nc Degrad ed c Non fatal As and De Analo g R T A Baseboard 1 5V P2 Memory AB VDDQ BB 1 5 P2MEM AB D A h All Voltage 02h Thresh old 01h u l c nc nc Degrad ed c Non fatal As and De Analo g R T A Baseboard 1 5V P2 Memory CD VDDQ BB 1 5 P2MEM CD D B h All Voltage 02h Thresh old 01h u l c nc nc Degrad ed c Non ...

Page 251: ...5V P2 Low Voltage Memory AB VDDQ BB 1 35 P2LV AB E 6h All Voltage 02h Thresh old 01h u l c nc nc Degrad ed c Non fatal As and De Analo g R T A Baseboard 1 35V P2 Low Voltage Memory CD VDDQ BB 1 35 P2LV CD E 7h All Voltage 02h Thresh old 01h u l c nc nc Degrad ed c Non fatal As and De Analo g R T A Baseboard 3 3V Riser 1 Power Good BB 3 3 RSR1 PGD E A h Platform Specific Voltage 02h Thresh old 01h ...

Page 252: ...sensors will be only present on systems with appropriate hardware to support redundancy for instance fan or power supply 4 This is only applicable when the system does not support redundant fans When fan redundancy is supported then the contribution to system state is driven by the fan redundancy sensor ...

Page 253: ... POST routine that was run prior to the error occurring helping to isolate the possible cause of the hang condition Each POST code is represented by eight LEDs four Green and four Amber The POST codes are divided into two nibbles an upper nibble and a lower nibble The upper nibble bits are represented by Amber Diagnostic LEDs 4 5 6 7 The lower nibble bits are represented by Green Diagnostics LEDs ...

Page 254: ...B initialization during Sec Phase 08h 0 0 0 0 1 0 0 0 Early NB initialization during Sec Phase 09h 0 0 0 0 1 0 0 1 End Of Sec Phase 0Eh 0 0 0 0 1 1 1 0 Microcode Not Found 0Fh 0 0 0 0 1 1 1 1 Microcode Not Loaded PEI Phase 10h 0 0 0 1 0 0 0 0 PEI Core 11h 0 0 0 1 0 0 0 1 CPU PEIM 15h 0 0 0 1 0 1 0 1 NB PEIM 19h 0 0 0 1 1 0 0 1 SB PEIM MRC Process Codes MRC Progress Code Sequence is executed PEI Ph...

Page 255: ... DXE USB start 9Bh 1 0 0 1 1 0 1 1 DXE USB reset 9Ch 1 0 0 1 1 1 0 0 DXE USB detect 9Dh 1 0 0 1 1 1 0 1 DXE USB enable A1h 1 0 1 0 0 0 0 1 DXE IDE begin A2h 1 0 1 0 0 0 1 0 DXE IDE reset A3h 1 0 1 0 0 0 1 1 DXE IDE detect A4h 1 0 1 0 0 1 0 0 DXE IDE enable A5h 1 0 1 0 0 1 0 1 DXE SCSI begin A6h 1 0 1 0 0 1 1 0 DXE SCSI reset A7h 1 0 1 0 0 1 1 1 DXE SCSI detect A8h 1 0 1 0 1 0 0 0 DXE SCSI enable A...

Page 256: ...ng memory initialization Progress Codes and Fatal Error Codes The MRC Progress Codes are displays to the Diagnostic LEDs that show the execution point in the MRC operational path at each step Table 74 MRC Progress Codes Checkpoint Diagnostic LED Decoder Description 1 LED On 0 LED Off Upper Nibble Lower Nibble MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h LED 7 6 5 4 3 2 1 0 MRC Progress Codes B0h 1 0 1 1 0 0 0 ...

Page 257: ...e lists all MRC fatal errors that are displayed to the Diagnostic LEDs Table 75 POST Progress LED Codes Checkpoint Diagnostic LED Decoder Description 1 LED On 0 LED Off Upper Nibble Lower Nibble MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h LED 7 6 5 4 3 2 1 0 MRC Fatal Error Codes E8h 1 1 1 0 1 0 0 0 No usable memory error 01h No memory was detected from the SPD read or invalid config that causes no operable m...

Page 258: ...h 2h 1h LED 7 6 5 4 3 2 1 0 EDh 1 1 1 0 1 1 0 1 DIMM configuration population error 01h Different DIMM types UDIMM RDIMM LRDIMM are detected installed in the system 02h Violation of DIMM population rules 03h The 3rd DIMM slot cannot be populated when QR DIMMs are installed 04h UDIMMs are not supported in the 3rd DIMM slot 05h Unsupported DIMM Voltage EFh 1 1 1 0 1 1 1 1 Indicates a CLTT table stru...

Page 259: ...e BIOS setup does not have any effect on this error Major The error message is displayed on the Error Manager screen and an error is logged to the SEL The POST Error Pause option setting in the BIOS setup determines whether the system pauses to the Error Manager for this type of error so the user can take immediate corrective action or the system continues booting Note For 0048 Password check fail...

Page 260: ...failed Self Test BIST Major 8172 Processor 03 failed Self Test BIST Major 8173 Processor 04 failed Self Test BIST Major 8180 Processor 01 microcode update not found Minor 8181 Processor 02 microcode update not found Minor 8182 Processor 03 microcode update not found Minor 8183 Processor 04 microcode update not found Minor 8190 Watchdog timer failed on last boot Major 8198 OS boot watchdog timer fa...

Page 261: ... 8536 DIMM_H2 failed test initialization Major 8537 DIMM_H3 failed test initialization Major 8538 DIMM_I1 failed test initialization Major 8539 DIMM_I2 failed test initialization Major 853A DIMM_I3 failed test initialization Major 853B DIMM_J1 failed test initialization Major 853C DIMM_J2 failed test initialization Major 853D DIMM_J3 failed test initialization Major 853E DIMM_K1 failed test initia...

Page 262: ...ection SPD failure Major 856B DIMM_D3 encountered a Serial Presence Detection SPD failure Major 856C DIMM_E1 encountered a Serial Presence Detection SPD failure Major 856D DIMM_E2 encountered a Serial Presence Detection SPD failure Major 856E DIMM_E3 encountered a Serial Presence Detection SPD failure Major 856F DIMM_F1 encountered a Serial Presence Detection SPD failure Major 8570 DIMM_F2 encount...

Page 263: ...d Major 85D2 DIMM_L2 disabled Major 85D3 DIMM_L3 disabled Major 85D4 DIMM_M1 disabled Major 85D5 DIMM_M2 disabled Major 85D6 DIMM_M3 disabled Major 85D7 DIMM_N1 disabled Major 85D8 DIMM_N2 disabled Major 85D9 DIMM_N3 disabled Major 85DA DIMM_O1 disabled Major 85DB DIMM_O2 disabled Major 85DC DIMM_O3 disabled Major 85DD DIMM_P1 disabled Major 85DE DIMM_P2 disabled Major 85DF DIMM_P3 disabled Major ...

Page 264: ... Option ROM Minor POST Error Beep Codes The following table lists the POST error beep codes Prior to system video initialization the BIOS uses these beep codes to inform users on error conditions The beep code is followed by a user visible code on the POST Progress LEDs Table 77 POST Error Beep Codes Beeps Error Message POST Progress Code Description 1 USB device action NA Short beep sounded whene...

Page 265: ...has incompatible power capabilities 1 5 4 2 Power fault DC power unexpectedly lost power good dropout Power unit sensors report power unit failure offset 1 5 4 4 Power control fault power good assertion timeout Power good assertion timeout Power unit sensors report soft power control failure offset 1 5 1 2 VR Watchdog Timer sensor assertion VR controller DC power on sequence was not completed in t...

Page 266: ...he Intel Server Board S1200V3RP supports up to 95W TDP Intel Xeon Processor Table 79 Compatible Intel Server Chassis P4000S family Intel Server Chassis SKU System Fans Storage Drives Power Supply s P4304XXSHDR Two Fixed Fans Four 3 5 Hotswap Drive Bay Two 460W CRPS P4304XXSFDR Two Fixed Fans Four 3 5 Fixed Drive Trays Two 460W CRPS You must install the active processor heat sink with the airflow d...

Page 267: ...re other CBCs Together they bridge the IPMB buses of multiple chassis CLI Command line interface CLTT Closed loop thermal throttling memory throttling mode CMOS In terms of this specification this describes the PC AT compatible region of battery backed 128 bytes of memory on the server board CSR Control and status register D cache Data cache Processor local cache dedicated for memory locations exp...

Page 268: ... Output buffer OEM Original equipment manufacturer OLTT Open loop thermal throttling memory throttling mode PCI Peripheral Component Interconnect PECI Platform Environmental Control Interface PEF Platform event filtering PET Platform event trap PIA Platform information area PLD Programmable logic device POST Power on self test PROM Programmable read only memory PSMI Power Supply Management Interfa...

Page 269: ...s that provides positive addressing for devices and bus arbitration SMI Server management interrupt SMI is the highest priority non maskable interrupt SMM Server management mode SMS Server management software SNMP Simple Network Management Protocol SOL Serial over LAN SPT Straight pass through SRAM Static random access memory UART Universal asynchronous receiver and transmitter UDP User Datagram P...

Page 270: ...ersion 2 0 2004 Intel Corporation Hewlett Packard Company NEC Corporation Dell Computer Corporation Platform Support for Serial over LAN SOL TMode and Terminal Mode External Architecture Specification Version 1 1 02 01 02 Intel Corporation Intel Remote Management Module User s Guide Intel Corporation Alert Standard Format ASF Specification Version 2 0 23 April 2003 2000 2003 Distributed Management...

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