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Intel BFCBASE - Motherboard - 7300 Datasheet Download Page 108

Thermal Specifications

108

Document Number: 318080-002

6.3.1.2

Processor Thermal Data Sample Rate and Filtering

The DTS (Digital Thermal Sensors) provide an improved capability to monitor device 
hot spots, which inherently leads to more varying temperature readings over short 
time intervals. The DTS sample interval range can be modified, and a data filtering 
algorithm can be activated to help moderate this. The DTS sample interval range is 82 
us (default) to 20 ms (max). This value can be set in BIOS.

To reduce the sample rate requirements on PECI and improve thermal data stability vs. 
time the processor DTS also implements an averaging algorithm that filters the 
incoming data. This is an alpha-beta filter with coefficients of 0.5, and is expressed 
mathematically as: Current_filtered_temp = (Previous_filtered_temp / 2) + 
(new_sensor_temp / 2). This filtering algorithm is fixed and cannot be changed. It is on 
by default and can be turned off in BIOS.

Host controllers should utilize the min/max sample times to determine the appropriate 
sample rate based on the controller's fan control algorithm and targeted response rate. 
The key items to take into account when settling on a fan control algorithm are the DTS 
sample rate, whether the temperature filter is enabled, how often the PECI host will 
poll the processor for temperature data, and the rate at which fan speed is changed. 
Depending on the designer’s specific requirements the DTS sample rate and alpha-beta 
filter may have no effect on the fan control algorithm. 

6.3.2

PECI Specifications

6.3.2.1

PECI Device Address

The Intel

®

 Xeon

®

 Processor 7200 Series and 7300 Series obtains its PECI address 

based on the processor APIC ID[4:2] at power on. APIC ID[4:3] is also known as 
Cluster ID[1:0] and APIC ID[2] is also known as Agent ID[1]. Cluster ID[1:0] is set by 
the chipset driven power-on configuration (POC) signals A[12:11]#. 

Table 6-9

 shows 

how the Agent ID is generated for each of the die based on the BREQ# signals asserted 
during power on for the Intel

®

 Xeon

®

 Processor 7200 Series and 7300 Series. 

Figure 6-8. Conceptual Fan Control Diagram For a PECI-Based Platform

Fan Speed

(RPM)

(not intended to depict actual implementation)

Max

Min

Temperature

PECI = -10

PECI = -20

TCC Activation 

Temperature

T

CONTROL

Setting

PECI = 0

Fan Speed

(RPM)

(not intended to depict actual implementation)

Max

Min

Temperature

PECI = -10

PECI = -20

TCC Activation 

Temperature

T

CONTROL

Setting

PECI = 0

Summary of Contents for BFCBASE - Motherboard - 7300

Page 1: ...ies and 7300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Intel Xeon Processor 7200 Series and 7300 Series Datasheet September 2008 ...

Page 2: ...l Xeon Processor 7200 Series and 7300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering numb...

Page 3: ...rboard Guidelines FMB 25 2 11 2 Platform Environmental Control Interface PECI DC Specifications 35 2 11 3 VCC Overshoot Specification 37 2 11 4 AGTL FSB Specifications 38 2 12 Front Side Bus AC Specifications 40 2 13 Processor AC Timing Waveforms 45 3 Mechanical Specifications 57 3 1 Package Mechanical Drawing 57 3 2 Processor Component Keepout Zones 60 3 3 Package Loading Specifications 66 3 4 Pa...

Page 4: ...xtended HALT Snoop or HALT Snoop State Stop Grant Snoop State 115 7 3 Enhanced Intel SpeedStep Technology 115 7 4 System Management Bus SMBus Interface 116 7 4 1 SMBus Device Addressing 117 7 4 2 PIROM and Scratch EEPROM Supported SMBus Transactions 118 7 4 3 Processor Information ROM PIROM 119 7 4 4 Checksums 137 7 4 5 Scratch EEPROM 137 8 Boxed Processor Specifications 139 8 1 Introduction 139 8...

Page 5: ...s 2X Address Timing Waveform 49 2 18 FSB Source Synchronous 4X Data Timing Waveform 50 2 19 TAP Valid Delay Timing Waveform 51 2 20 Test Reset TRST Async GTL Input and PROCHOT Timing Waveform 51 2 21 THERMTRIP Power Down Sequence 51 2 22 SMBus Timing Waveform 52 2 23 SMBus Valid Delay Timing Waveform 52 2 24 Voltage Sequence Timing Requirements 53 2 25 FERR PBE Valid Delay Timing 54 2 26 VID Step ...

Page 6: ...Differential Clock AC Specifications 40 2 20 Front Side Bus Common Clock AC Specifications 40 2 21 FSB Source Synchronous AC Specifications 41 2 22 Miscellaneous GTL AC Specifications 42 2 23 Front Side Bus AC Specifications Reset Conditions 42 2 24 TAP Signal Group AC Specifications 42 2 25 VID Signal Group AC Specifications 44 2 26 SMBus Signal Group AC Specifications 44 3 1 Processor Loading Sp...

Page 7: ...2 7 7 2 Extended HALT Maximum Power 113 7 3 Memory Device SMBus Addressing 118 7 4 Read Byte SMBus Packet 118 7 5 Write Byte SMBus Packet 118 7 6 Processor Information ROM Data Sections 119 7 7 128 Byte ROM Checksum Values 137 ...

Page 8: ...ng fields SQNUM S Spec QDF Number PREV Package Revision PPN Processor Part Number Updated the Processor Mechanical drawings to add an optional small shallow depression in the top right hand side corner of the integrated heat spreader IHS This feature which supports anti mixing may be seen on some processor packages There are no major electrical mechanical or thermal differences in the form fit or ...

Page 9: ...d Intel SpeedStep Technology TM1 and TM2 provide efficient and effective cooling in high temperature situations Enhanced Intel SpeedStep Technology allows trade offs to be made between performance and power consumption This may lower average power consumption in conjunction with OS support The Intel Xeon Processor 7200 Series and 7300 Series features include Advanced Dynamic Execution enhanced flo...

Page 10: ...t core voltage VCC power planes for each processor FSB termination voltage VTT is shared and must connect to all FSB agents The processor core voltage utilizes power delivery guidelines specified by VRM EVRD 11 0 and its associated load line see Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for further details VRM EVRD 11 0 will support the power re...

Page 11: ...ugh this surface mount 604 pin zero insertion force ZIF socket Processor core Processor core with integrated L1 cache L2 cache and system bus interface are shared between the two cores on the die All AC timing and signal integrity specifications are at the pads of the processor die FSB Front Side Bus The electrical interface that connects the processor to the chipset Also referred to as the proces...

Page 12: ...nt of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface Thermal Design Power Processor thermal solutions should be designed to meet this target It is the highest expected sustainable power while running known power intensive real applications TDP is not the maximum power that the processor can di...

Page 13: ...l 64 Software Developer s Manual Documentation Changes 252046 1 IA 32 Intel Architecture Optimization Reference Manual 248966 1 Intel Extended Memory 64 Technology Volume I Volume 2 300834 300835 1 Intel Virtualization Technology for IA 32 Processors VT x Preliminary Specification C97063 1 Dual Core Intel Xeon Processor 7200 Series and Quad Core Intel Xeon Processor 7300 Series Specification Updat...

Page 14: ...Introduction 14 Document Number 318080 002 ...

Page 15: ...TA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END must be generated on the baseboard See Table 2 17 for GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END specifications Refer to the applicable platform design guidelines for details Termination resistors RTT for AGTL signals are provided on the processor silicon and are terminated to VTT The on die termination resistors are a...

Page 16: ... required high frequency decoupling capacitance on the processor package However additional high frequency capacitance must be added to the baseboard to properly decouple the return currents from the FSB Bulk decoupling must also be provided by the baseboard for proper AGTL bus operation Decoupling guidelines are described in the appropriate platform design guidelines 2 3 Front Side Bus Clock BCLK...

Page 17: ...opriate platform design guidelines for further details 2 3 2 PLL Power Supply An on die PLL filter solution is implemented on the processor The VCCPLL input is used to provide power to the on chip PLL of the processor Please refer to Table 2 9 for DC specifications Refer to the appropriate platform design guidelines for decoupling and routing guidelines 2 4 Voltage Identification VID The Voltage I...

Page 18: ...RD 11 0 Design Guidelines for further details Although the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines defines VID 7 0 VID 7 and VID 0 are not used on the Dual Core Intel Xeon Processor 7200 Series and Quad Core Intel Xeon Processor 7300 Series The Dual Core Intel Xeon Processor 7200 Series and Quad Core Intel Xeon Processor 7300 Series provides t...

Page 19: ... VID1 12 5 mV VCC_MAX 7A 1 1 1 1 0 1 0 8500 3C 0 1 1 1 1 0 1 2375 78 1 1 1 1 0 0 0 8625 3A 0 1 1 1 0 1 1 2500 76 1 1 1 0 1 1 0 8750 38 0 1 1 1 0 0 1 2625 74 1 1 1 0 1 0 0 8875 36 0 1 1 0 1 1 1 2750 72 1 1 1 0 0 1 0 9000 34 0 1 1 0 1 0 1 2875 70 1 1 1 0 0 0 0 9125 32 0 1 1 0 0 1 1 3000 6E 1 1 0 1 1 1 0 9250 30 0 1 1 0 0 0 1 3125 6C 1 1 0 1 1 0 0 9375 2E 0 1 0 1 1 1 1 3250 6A 1 1 0 1 0 1 0 9500 2C 0...

Page 20: ...latform design guidelines For each processor socket connect the TESTIN1 and TESTIN2 signals together then terminate the net with a 51 Ω resistor to VTT The TESTHI signal must be tied to the processor VTT using a matched resistor where a matched resistor has a resistance value within 20 of the impedance of the board transmission line traces For example if the trace impedance is 50 Ω then a value be...

Page 21: ...I O Synchronous to BCLK 1 0 ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 Open Drain Output Asynchronous FERR PBE IERR PROCHOT THERMTRIP TDO CMOS Asynchronous Input Asynchronous A20M FORCEPR IGNNE INIT LINT0 INTR LINT1 NMI PWRGOOD SMI STPCLK TCK TDI TMS TRST CMOS Asynchronous Output Asynchronous BSEL 2 0 VID 6 1 FSB Clock Clock BCLK 1 0 SMBus Synchronous to SM_CLK SM_CLK SM_DAT SM_EP_A 2 0 SM_WP Power Other Power...

Page 22: ...nts within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Similar considerations must be made for TCK TMS and TRST Two copies of each signal may be required with each driving a different voltage level Table 2 5 AGTL Signal Description Table AGTL signals with RTT 1 AGTL...

Page 23: ...tside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions fo...

Page 24: ...e specification for that parameter Unless otherwise noted all specifications in the tables apply to all frequencies and cache sizes See Section 5 for the pin signal definitions Most of the signals on the processor FSB are in the AGTL signal group The DC specifications for these signals are listed in Table 2 11 Table 2 9 through Table 2 17 list the DC specifications and are valid only while meeting...

Page 25: ... step size during a transition 12 5 mV VVID_SHIFT Total allowable DC load line shift from VID steps 450 mV 10 VTT FSB termination voltage DC AC specification 1 14 1 20 1 26 V 8 13 VCCPLL PLL supply voltage DC AC specification 1 425 1 50 1 605 V SM_VCC SMBus supply voltage 3 135 3 300 3 465 V ICC ICC for Quad Core Intel Xeon L7345 Processor with multiple VID Launch FMB 60 A 4 5 6 9 ICC_RESET ICC_RE...

Page 26: ...ese guidelines are for estimation purposes only See Section 2 11 1 for further details on FMB guidelines 7 This specification represents the total current for GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END 8 VTT must be provided via a separate voltage source and must not be connected to VCC This specification is measured at the pin ITT ICC for VTT supply before VCC stable ICC fo...

Page 27: ...efinitely Refer to Figure 2 9 for further details on the average processor current draw over various time durations This parameter is based on design characterization and is not tested 15 This is the maximum total current drawn from the VTT plane by only one processor with RTT enabled This specification does not include the current coming from on board termination RTT through the signal line Refer...

Page 28: ...cuitry should not trip for load currents greater than ICC_TDC 2 Not 100 tested Specified by design characterization Figure 2 2 Dual Core Dual Core Intel Xeon Processor 7200 Series Load Current versus Time 6 0 6 5 70 75 8 0 8 5 9 0 9 5 10 0 0 0 1 0 1 1 10 10 0 10 0 0 Time Duration s Sustained Current A Figure 2 3 Quad Core Intel Xeon Processor 7200 Series and 7300 Series Load Current versus Time 6 ...

Page 29: ...al protection circuitry should not trip for load currents greater than ICC_TDC 2 Not 100 tested Specified by design characterization Figure 2 4 Quad Core Intel Xeon X7350 Processor Load Current versus Time 10 0 10 5 110 115 12 0 12 5 13 0 0 0 1 0 1 1 10 10 0 10 0 0 Time Duration s Sustained Current A ...

Page 30: ...120 VID 0 150 VID 0 165 VID 0 180 1 2 3 4 5 125 VID 0 156 VID 0 171 VID 0 186 1 2 3 4 5 130 VID 0 163 VID 0 178 VID 0 193 1 2 3 4 5 Notes 1 The VCC_MIN and VCC_MAX loadlines represent static and transient limits Please see Section 2 11 3 for VCC overshoot specifications 2 This table is intended to aid in reading discrete points on Figure 2 5 for Intel Xeon Processor 7200 Series and 7300 Series Fig...

Page 31: ...feedback for voltage regulator circuits must also be taken from processor VCC_SENSE2 and VSS_SENSE2 pins Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for socket load line guidelines and VR implementation Please refer to the appropriate platform design guide for details on VR implementation Figure 2 5 Quad Core Intel Xeon Processor 7200...

Page 32: ...on feedback for voltage regulator circuits must also be taken from processor VCC_SENSE2 and VSS_SENSE2 pins Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for socket load line guidelines and VR implementation Please refer to the appropriate platform design guide for details on VR implementation Figure 2 6 Quad Core Intel Xeon X7350 Proce...

Page 33: ...egulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE2 and VSS_SENSE2 pins Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for socket load line guidelines and VR implementation Please refer to the appropriate platform design guide for details on VR implementation Figure 2 7 Quad Core Intel Xeon L734...

Page 34: ...tage level at a receiving agent that will be interpreted as a logical high value 4 VIH and VOH may experience excursions above VTT However input signal drivers must comply with the signal quality specifications 5 This is the pull down driver resistance Refer to processor I O Buffer Models for I V characteristics Measured at 0 31 VTT RON min 0 225 RTT RON typ 0 250 RTT RON max 0 275 RTT 6 GTLREF sh...

Page 35: ...ntal Control Interface PECI DC Specifications PECI is an Intel proprietary one wire bus interface that provides a communication channel between Intel processor and external thermal monitoring devices The Dual Core Intel Xeon Processor 7200 Series and Quad Core Intel Xeon Processor Table 2 12 CMOS Signal Input Output Group DC Specifications Symbol Parameter Min Typ Max Units Notes1 VIL Input Low Vo...

Page 36: ... VTT supplies the PECI interface PECI behavior does not affect VTT min max specifications 2 The leakage specification applies to powered devices on the PECI bus 3 One node is counted for each client and one node for the system host Extended trace lengths might appear as additional nodes 2 11 2 2 Input Device Hysteresis The input buffers in both client and host models must use a Schmitt triggered i...

Page 37: ...ove VID These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE pins and across the VCC_SENSE2 and VSS_SENSE2 pins Figure 2 9 Input Device Hysteresis Minimum VP Maximum VP Minimum VN Maximum VN PECI High Range PECI Low Range Valid Input Signal Range Minimum Hysteresis VTT PECI Ground Table 2 16 VCC Overshoot Specifications Symbol Parameter Min Max Uni...

Page 38: ...processor silicon See Table 2 6 for details on which signals do not include on die termination Please refer to Table 2 17 for RTT values Valid high and low levels are determined by the input buffers via comparing with a reference voltage called GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END GTLREF_DATA_MID and GTLREF_DATA_END are the reference voltage for the FSB 4X data signals...

Page 39: ...difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback 7 Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches It includes input threshold hysteresis 8 The crossing point must meet the absolute and relative crossing point specifications simultaneously 9 VHavg can be measured directly using Vt...

Page 40: ...r voltages In other words the largest absolute difference between adjacent clock periods must be less than the period stability 5 Rise and fall times are measured single ended between 245 mV and 455 mV of the clock swing 6 Measured from 200 mV to 200 mV The signal must be monotonic through the measurement region for rise and fall time The 400 mV measurement window is centered on the differential z...

Page 41: ...es for more information on the definitions and use of these specifications 9 This specification represents the minimum time the data or address will be valid after its strobe Refer to the appropriate platform design guidelines for more information on the definitions and use of these specifications 10 The rising edge of ADSTB must come approximately 1 2 BCLK period after the falling edge of ADSTB 1...

Page 42: ...nents being powered by it 11 The maximum PWRGOOD rise time specification denotes the slowest allowable rise time for the processor Measured between 0 3 VTT and 0 7 VTT 12 See Table 2 19 for BCLK specifications Notes 1 Before the clock that de asserts RESET 2 After the clock that de asserts RESET Table 2 22 Miscellaneous GTL AC Specifications T Parameter Min Max Unit Figure Notes 1 2 3 4 T35 Asynch...

Page 43: ...5 Referenced to the falling edge of TCK 6 TRST must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor 7 Specification for a minimum swing defined between TAP Vt to Vt This assumes a minimum edge rate of 0 5 V ns 8 It is recommended that TMS be asserted while TRST is being deasserted T57 TDI TMS Hold Time 7 5 ns 2 19 4 7 T58 TDO Clock to Output Delay 0 7 5 n...

Page 44: ...ion Table 2 25 VID Signal Group AC Specifications T Parameter Min Max Unit Figure Notes1 2 T80 VID Step Time 5 µs 2 27 T81 VID Dwell Time at 266 666 MHz FSB 500 µs 2 27 T82 VID Down Transition to Valid VCC min 0 µs 2 26 2 27 T83 VID Up Transition to Valid VCC min 50 µs 2 26 2 27 T84 VID Down Transition to Valid VCC max 50 µs 2 26 2 27 T85 VID Up Transition to Valid VCC max 0 µs 2 26 2 27 Table 2 2...

Page 45: ...ated data strobe Source synchronous address signals are referenced to the rising and falling edge of their associated address strobe All source synchronous AGTL signal timings are referenced at nominal GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END at the processor core pads 3 All AC timings for AGTL strobe signals are referenced to BCLK 1 0 at VCROSS All AGTL strobe signal timi...

Page 46: ...nt Number 318080 002 Figure 2 11 Electrical Test Circuit Figure 2 12 TCK Clock Waveform V2 V1 T p TCK Tp T55 Period V1 V2 For rise and fall times TCK is measured between 20 and 80 points on the waveform V3 TCK is referenced to 0 5 VTT V3 ...

Page 47: ...gback Margin Rising Edge Ringback Falling Edge Ringback BCLK0 BCLK1 Crossing Voltage Tp Tp T1 BCLK 1 0 period Figure 2 14 Differential Clock Crosspoint Specification 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 200 250 300 350 400 450 500 550 600 650 VHavg mV Crossing Point mV 550 mV 250 mV 250 0 5 VHavg 700 550 0 5 VHavg 700 ...

Page 48: ... and meg indicates mv ns units 4 Waveform at pad has faster edge rate than at pin Figure 2 15 BCLK Waveform at Processor Pad and Pin Figure 2 16 FSB Common Clock Valid Delay Timing Waveform BCLK0 BCLK1 Common Clock Signal driver Common Clock Signal receiver T0 T1 T2 TQ TR valid valid valid TP TP T10 Common Clock Output Valid Delay TQ T11 Common Clock Input Setup TR T12 Common Clock Input Hold Time...

Page 49: ...valid valid valid TM TN TK TS TH TJ TH TJ TH T23 Source Sync Address Output Valid Before Address Strobe TJ T24 Source Sync Address Output Valid After Address Strobe TK T27 Source Sync Address Strobe Setup Time to BCLK TM T25 Source Sync Input Setup Time TN T26 Source Sync Input Hold Time TS T20 Source Sync Output Valid Delay TP T1 BCLK 1 0 Period TR TR T31 Address Strobe Output Valid Delay T0 T1 T...

Page 50: ...DSTBn receiver TE TG TE TG TA TB TA TB TD TC TA T21 Source Sync Data Output Valid Delay Before Data Strobe TB T22 Source Sync Data Output Valid Delay After Data Strobe TC T28 Source Sync Data Strobe Setup Time to BCLK TD T30 Data Strobe n DSTBN Output Valid Delay TE T25 Source Sync Input Setup Time TG T26 Source Sync Input Hold Time TJ T20 Source Sync Data Output Valid Delay TP T1 BCLK 1 0 Period ...

Page 51: ... Valid Delay Timing Waveform Tx T58 TDO Clock to Output Delay Ts T56 TDI TMS Setup Time Th T57 TDI TMS Hold Time V 0 5 VTT TCK Signal Tx Ts Th V Valid V Figure 2 20 Test Reset TRST Async GTL Input and PROCHOT Timing Waveform V Tq T q T59 TRST Pulse Width V 0 5 VTT T38 PROCHOT Pulse Width V GTLREF Figure 2 21 THERMTRIP Power Down Sequence THERMTRIP Vcc VTT TA TA T39 THERMTRIP to removal of power ...

Page 52: ...TOP STOP START START t LOW t R t HD STA t HD DAT tBUF HIGH t t SU DAT t t SU STA t HD STA SU STO t F t LOW t HIGH t R t F t HD STA t HD DAT t BUF t SU DAT t SU STA t SU STD T97 T99 T95 T94 T92 T93 T102 T101 T98 T100 Figure 2 23 SMBus Valid Delay Timing Waveform DATA OUTPUT DATA VALID SM_CLK SM_DAT TAA TAA T96 ...

Page 53: ...T stable to VID 6 1 BSEL 2 0 valid Td T36 PWRGOOD assertion to RESET de assertion Te T41 VCC stable to PWRGOOD assertion Tf T37 BCLK stable to PWRGOOD assertion Tg T49 VCCPLL stable to PWRGOOD assertion Th T45 Reset Configuration Signals A 35 3 BR 1 0 INIT SMI Setup Time Ti T46 Reset Configuration Signals A 35 3 INIT SMI Hold Time Tj T47 Reset Configuration Signals BR 1 0 Hold Time Th Ti Tj Reset ...

Page 54: ...a period of Ta from STPCLK deassertion Inside these undefined regions the PBE signal is driven FERR is driven at all other times Figure 2 25 FERR PBE Valid Delay Timing BCLK STPCLK System bus FERR PBE SG Ack FERR undefined FERR Ta PBE undefined Figure 2 26 VID Step Timings VID n n 1 m 1 m Ta Tb Tc Td Ta T84 VID Down to Valid VCC max Tb T82 VID Down to Valid VCC min Tc T85 VID Up to Valid VCC max T...

Page 55: ...e Tb T81 Thermal Monitor 2 Dwell Time Tc T84 VID Down to Valid VCC max Td T82 VID Down to Valid VCC min Te T85 VID Up to Valid VCC max Tf T83 VID Up to Valid VCC min n 5 n 5 Note This waveform illustrates an example of an Intel Thermal Monitor 2 transition or an Intel Enhanced SpeedStep Technology transition that is six VID steps down from the current state and six steps back up Any arbitrary up o...

Page 56: ...Electrical Specifications 56 Document Number 318080 002 ...

Page 57: ...cket Design Guidelines for complete details on the mPGA604 socket The package components shown in Figure 3 1 include the following 1 IHS 2 Processor die 3 FC mPGA6 package 4 Pin side capacitors 5 Package pin Note Figure 3 1 is not to scale and is for reference only The mPGA604 socket is not shown 3 1 Package Mechanical Drawing The package mechanical drawings are shown in Figure 3 2 and Figure 3 3 ...

Page 58: ...Mechanical Specifications 58 Document Number 318080 002 Figure 3 2 Processor Package Drawing Sheet 1 of 2 ...

Page 59: ...Document Number 318080 002 59 Mechanical Specifications Figure 3 3 Processor Package Drawing Sheet 2 of 2 ...

Page 60: ...in components on the substrate that define component keepout zone requirements A thermal and mechanical solution design must not intrude into the required keepout zones Decoupling capacitors are typically mounted to either the topside or pin side of the package substrate See Figure 3 4 and Figure 3 5 for keepout zones ...

Page 61: ...Document Number 318080 002 61 Mechanical Specifications Figure 3 4 Top Side Board Keepout Zones Part 1 ...

Page 62: ...Mechanical Specifications 62 Document Number 318080 002 Figure 3 5 Top Side Board Keepout Zones Part 2 ...

Page 63: ...Document Number 318080 002 63 Mechanical Specifications Figure 3 6 Bottom Side Board Keepout Zones ...

Page 64: ...Mechanical Specifications 64 Document Number 318080 002 Figure 3 7 Board Mounting Hole Keepout Zones ...

Page 65: ...Document Number 318080 002 65 Mechanical Specifications Figure 3 8 Volumetric Height Keep Ins ...

Page 66: ...ed on limited testing for design characterization Loading limits are for the package only and do not include the limits of the processor socket 4 This specification applies for thermal retention solutions that allow baseboard deflection 44 10 288 65 N lbf 1 2 3 5 5 This specification applies either for thermal retention solutions that prevent baseboard deflection or for the Intel enabled reference...

Page 67: ...ass weight includes all the components that are included in the package 3 7 Processor Materials Table 3 3 lists some of the package components and associated materials Table 3 2 Package Handling Guidelines Parameter Maximum Recommended Notes Shear 356 N 80 lbf 1 2 Notes 1 A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface 2 These guidelines are base...

Page 68: ...t height 1 43 mm 56 mils width 0 95 mm 37 5 mils Figure 3 9 Processor Topside Markings INTEL XEON i M YY PbFree symbol 2D Matrix FPO Serial Pin 1 Indicator INTEL XEON i M YY PbFree symbol 2D Matrix FPO Serial Pin 1 Indicator Figure 3 10 Processor Bottom Side Markings X7350 2933MP 8M 1066 SLA67 COSTA RICA C0096109 0021 Processor Speed Cache Bus Number S Spec Country of Assy FPO Serial 13 Characters...

Page 69: ...nt to identify processor pins Figure 3 11 Processor Pin Out Coordinates Top View Vcc Vss ADDRESS DATA Vcc Vss CLOCKS COMMON CLOCK COMMON CLOCK Async JTAG Processor Top View Signal VCC Ground Reserved No Connect A C E G J L N R U W AA AC AE B D F H K M P T V Y AB AD 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 1 VTT A C E G J L N R U W AA AC AE B D F H K M P T V Y AB AD 2 4 6 8 10 12 14 16 18 20 22 24 ...

Page 70: ...Mechanical Specifications 70 Document Number 318080 002 ...

Page 71: ...ource Sync Input Output A21 B10 Source Sync Input Output A22 B11 Source Sync Input Output A23 C12 Source Sync Input Output A24 E14 Source Sync Input Output A25 D13 Source Sync Input Output A26 A9 Source Sync Input Output A27 B8 Source Sync Input Output A28 E13 Source Sync Input Output A29 D12 Source Sync Input Output A30 C11 Source Sync Input Output A31 B7 Source Sync Input Output A32 A6 Source Sy...

Page 72: ...ut Table 4 1 Pin Listing by Pin Name Sheet 3 of 16 Pin Name Pin No Signal Buffer Type Direction D29 AD21 Source Sync Input Output D30 AD19 Source Sync Input Output D31 AB17 Source Sync Input Output D32 AB16 Source Sync Input Output D33 AA16 Source Sync Input Output D34 AC17 Source Sync Input Output D35 AE13 Source Sync Input Output D36 AD18 Source Sync Input Output D37 AB15 Source Sync Input Outpu...

Page 73: ...nput Output MCERR D7 Common Clk Input Output PECI C28 Power Other Input Output PROC_ID0 A30 Power Other Output PROC_ID1 B29 Power Other Output PROCHOT B25 Async GTL Output PWRGOOD AB7 Async GTL Input REQ0 B19 Source Sync Input Output REQ1 B21 Source Sync Input Output Table 4 1 Pin Listing by Pin Name Sheet 5 of 16 Pin Name Pin No Signal Buffer Type Direction REQ2 C21 Source Sync Input Output REQ3 ...

Page 74: ...Other VCC G4 Power Other VCC G6 Power Other VCC G8 Power Other Table 4 1 Pin Listing by Pin Name Sheet 7 of 16 Pin Name Pin No Signal Buffer Type Direction VCC G24 Power Other VCC G26 Power Other VCC G28 Power Other VCC G30 Power Other VCC H1 Power Other VCC H3 Power Other VCC H5 Power Other VCC H7 Power Other VCC H9 Power Other VCC H23 Power Other VCC H25 Power Other VCC H27 Power Other VCC H29 P...

Page 75: ...her VCC T4 Power Other Table 4 1 Pin Listing by Pin Name Sheet 9 of 16 Pin Name Pin No Signal Buffer Type Direction VCC T6 Power Other VCC T8 Power Other VCC T24 Power Other VCC T26 Power Other VCC T28 Power Other VCC T30 Power Other VCC U1 Power Other VCC U3 Power Other VCC U5 Power Other VCC U7 Power Other VCC U9 Power Other VCC U23 Power Other VCC U25 Power Other VCC U27 Power Other VCC U29 Pow...

Page 76: ... VSS C25 Power Other VSS C29 Power Other VSS D2 Power Other VSS D5 Power Other Table 4 1 Pin Listing by Pin Name Sheet 11 of 16 Pin Name Pin No Signal Buffer Type Direction VSS D11 Power Other VSS D21 Power Other VSS D28 Power Other VSS D30 Power Other VSS E1 Power Other VSS E9 Power Other VSS E15 Power Other VSS E17 Power Other VSS E23 Power Other VSS E29 Power Other VSS E31 Power Other VSS F2 Po...

Page 77: ...wer Other VSS N30 Power Other Table 4 1 Pin Listing by Pin Name Sheet 13 of 16 Pin Name Pin No Signal Buffer Type Direction VSS P1 Power Other VSS P3 Power Other VSS P5 Power Other VSS P7 Power Other VSS P9 Power Other VSS P23 Power Other VSS P25 Power Other VSS P27 Power Other VSS P29 Power Other VSS P31 Power Other VSS R2 Power Other VSS R4 Power Other VSS R6 Power Other VSS R8 Power Other VSS R...

Page 78: ...wer Other VSS AC25 Power Other Table 4 1 Pin Listing by Pin Name Sheet 15 of 16 Pin Name Pin No Signal Buffer Type Direction VSS AD3 Power Other VSS AD9 Power Other VSS AD15 Power Other VSS AD17 Power Other VSS AD23 Power Other Vss AE6 Power Other VSS AE11 Power Other VSS AE21 Power Other VSS AE27 Power Other VSS_SENSE D26 Power Other Output VSS_SENSE2 B26 Power Other Output VTT A4 Power Other VTT...

Page 79: ...nput Output B9 VSS Power Other B10 A21 Source Sync Input Output B11 A22 Source Sync Input Output B12 VTT Power Other B13 A13 Source Sync Input Output B14 A12 Source Sync Input Output B15 VSS Power Other B16 A11 Source Sync Input Output B17 VSS Power Other B18 A5 Source Sync Input Output B19 REQ0 Common Clk Input Output B20 VCC Power Other B21 REQ1 Common Clk Input Output B22 REQ4 Common Clk Input ...

Page 80: ...able 4 2 Pin Listing by Pin Number Sheet 3 of 14 Pin No Pin Name Signal Buffer Type Direction E5 IERR Async GTL Output E6 VCC Power Other E7 BPM2 Common Clk Input Output E8 BPM4 Common Clk Input Output E9 VSS Power Other E10 AP0 Common Clk Input Output E11 VTT Power Other E12 VTT Power Other E13 A28 Source Sync Input Output E14 A24 Source Sync Input Output E15 VSS Power Other E16 COMP1 Power Other...

Page 81: ...er Other H23 VCC Power Other H24 VSS Power Other H25 VCC Power Other Table 4 2 Pin Listing by Pin Number Sheet 5 of 14 Pin No Pin Name Signal Buffer Type Direction H26 VSS Power Other H27 VCC Power Other H28 VSS Power Other H29 VCC Power Other H30 VSS Power Other H31 VCC Power Other J1 VSS Power Other J2 VCC Power Other J3 VSS Power Other J4 VCC Power Other J5 VSS Power Other J6 VCC Power Other J7...

Page 82: ...her N23 VCC Power Other Table 4 2 Pin Listing by Pin Number Sheet 7 of 14 Pin No Pin Name Signal Buffer Type Direction N24 VSS Power Other N25 VCC Power Other N26 VSS Power Other N27 VCC Power Other N28 VSS Power Other N29 VCC Power Other N30 VSS Power Other N31 VCC Power Other P1 VSS Power Other P2 VCC Power Other P3 VSS Power Other P4 VCC Power Other P5 VSS Power Other P6 VCC Power Other P7 VSS ...

Page 83: ... 14 Pin No Pin Name Signal Buffer Type Direction V9 VSS Power Other V23 VSS Power Other V24 VCC Power Other V25 VSS Power Other V26 VCC Power Other V27 VSS Power Other V28 VCC Power Other V29 VSS Power Other V30 VCC Power Other V31 VSS Power Other W1 VCC Power Other W2 VSS Power Other W3 TESTHI1 Power Other Input W4 VSS Power Other W5 BCLK1 FSB Clk Input W6 VTT Power Other W7 VTT Power Other W8 VT...

Page 84: ...SM_EP_A0 SMBus Input Table 4 2 Pin Listing by Pin Number Sheet 11 of 14 Pin No Pin Name Signal Buffer Type Direction AA30 VSS Power Other AA31 VCC Power Other AB1 VSS Power Other AB2 VCC Power Other AB3 BSEL1 Power Other Output AB4 Reserved AB5 VSS Power Other AB6 D63 Source Sync Input Output AB7 PWRGOOD Async GTL Input AB8 VCC Power Other AB9 DBI3 Source Sync Input Output AB10 D55 Source Sync Inp...

Page 85: ...ut AD20 VCC Power Other Table 4 2 Pin Listing by Pin Number Sheet 13 of 14 Pin No Pin Name Signal Buffer Type Direction AD21 D29 Source Sync Input Output AD22 DBI1 Source Sync Input Output AD23 VSS Power Other AD24 D21 Source Sync Input Output AD25 D18 Source Sync Input Output AD26 VCC Power Other AD27 D4 Source Sync Input Output AD28 Reserved AD29 SM_WP SMBus Input AD30 Reserved AD31 Reserved AE2...

Page 86: ...Pin Listing 86 Document Number 318080 002 ...

Page 87: ...robe is asserted to indicate the validity of the transaction address on the A 39 3 pins All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction This signal must be connected to the appropriate pins on all Intel Xeon Processor 7200 Series and 7300 Series FSB agents AD...

Page 88: ...determine processor debug readiness BPM5 provides PREQ Probe Request functionality for the TAP port PREQ is used by debug tools to request debug operation of the processors BPM 5 4 must be bussed to all bus agents Please refer to the appropriate platform design guidelines for more detailed information BPMb3 BPMb 2 1 BPMb0 I O O I O BPMb 3 0 Breakpoint Monitor are a second set of breakpoint and per...

Page 89: ...invert the data bus signals for that particular sub phase for that 16 bit group DBSY I O DBSY Data Bus Busy is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must connect the appropriate pins on all processor FSB agents DEFER I DEFER is asserted by an agent to indicate tha...

Page 90: ...REF_ADD_MID GTLREF_ADD_END I GTLREF_ADD determines the signal reference level for AGTL address and common clock input pins GTLREF_ADD is used by the AGTL receivers to determine if a signal is a logical 0 or a logical 1 Please refer to Table 2 17 and the appropriate platform design guidelines for additional details GTLREF_DATA_MID GTLREF_DATA_END I GTLREF_DATA determines the signal reference level ...

Page 91: ...eries package LOCK I O LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of all processor FSB agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the processor FSB it will wait u...

Page 92: ...e response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of all processor FSB agents RSP I RSP Response Parity is driven by the response agent the agent responsible for completion of the current transaction during assertion of RS 2 0 the signals for which RSP provides parity protection It must connect to the appropriate pins of all proc...

Page 93: ...HERMTRIP Thermal Trip indicates the processor junction temperature has reached a temperature beyond which permanent silicon damage may occur Measurement of the temperature is accomplished through an internal thermal sensor Upon assertion of THERMTRIP the processor will shut off its internal clocks thus halting program execution in an attempt to reduce the processor junction temperature To protect ...

Page 94: ...hese pins or disable itself VSS_SENSE VSS_SENSE2 O VSS_SENSE and VSS_SENSE2 provides an isolated low impedance connection to the processor core power and ground These signals should be used to provide feedback to the voltage regulator signals which ensure the output voltage that is processor voltage remains within specification Please see the applicable platform design guide for implementation det...

Page 95: ...ore Intel Xeon X7350 Processor Table 6 5 and Figure 6 3 for Quad Core Intel Xeon L7345 Processor Table 6 7 and Figure 6 4 for Dual Core Intel Xeon Processor 7200 Series Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design please refer to the Dual Core Intel Xeon Proces...

Page 96: ...cause the processor to consume maximum power dissipation for sustained time periods Intel recommends that complete thermal solution designs target the Thermal Design Power TDP instead of the maximum processor power consumption The Thermal Monitor feature is intended to help protect the processor in the event that an application exceeds the TDP recommendation for a sustained time period For more de...

Page 97: ...imum TCASE 4 These specifications are based pre silicon estimates and simulations These specifications will be updated with characterized data from silicon measurements in a future release of this document 5 Power specifications are defined at all VIDs found in Table 2 3 The Quad Core Intel Xeon E7300 Processor may be shipped under multiple VIDs for each frequency 6 FMB or Flexible Motherboard gui...

Page 98: ...y 6 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements Notes 1 Thermal Profile is representative of a volumetrically unconstrained platform Please refer to Table 6 4 for discrete points that constitute the thermal profile 2 Implementation of Thermal Profile should result in virtually no TCC activation Furthermore utilization of t...

Page 99: ...ASE 4 These specifications are based on initial silicon characterization These specifications may be further updated as more characterization data becomes available 5 Power specifications are defined at all VIDs found in Table 2 3 The Quad Core Intel Xeon L7345 Processor may be shipped under multiple VIDs for each frequency 6 FMB or Flexible Motherboard guidelines provide a design target for meeti...

Page 100: ...l Mechanical Design Guide for system and environmental implementation details Figure 6 3 Quad Core Intel Xeon L7345 Processor Thermal Profile Thermal Profile 20 0 25 0 30 0 35 0 40 0 45 0 50 0 55 0 60 0 65 0 70 0 0 5 10 15 20 25 30 35 40 45 50 Power W Temperature C Tcase 0 420 x Power 45 Table 6 6 Quad Core Intel Xeon L7345 Processor Thermal Profile Power W TCASE_MAX C 0 45 0 5 47 1 10 49 2 15 51 ...

Page 101: ...at all VIDs found in Table 2 3 The Dual Core Intel Xeon Processor 7200 Series may be shipped under multiple VIDs for each frequency 6 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements Notes 1 Please refer to Table 6 8 for discrete points that constitute the thermal profile 2 Implementation of Thermal Profile should result in vir...

Page 102: ...ch frequency 6 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements 6 1 2 Thermal Metrology The minimum and maximum case temperatures TCASE are specified in Table 6 2 through Table 6 8 and are measured at the geometric top center of the processor integrated heat spreader IHS Figure 6 5 illustrates the location where TCASE temperatu...

Page 103: ...ximum operating temperature The TCC reduces processor power consumption as needed by modulating starting and stopping the internal processor core clocks The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that th...

Page 104: ...operating within specifications TM2 requires support for dynamic VID transitions in the platform Note Not all Intel Xeon Processor 7200 Series and 7300 Series are capable of supporting TM2 When Thermal Monitor 2 is enabled and a high temperature situation is detected the Thermal Control Circuit TCC will be activated for all processor cores The TCC causes the processor to adjust its operating frequ...

Page 105: ...he processor to reduce its power consumption This mechanism is referred to as On Demand mode and is distinct from the Thermal Monitor and Thermal Monitor 2 features On Demand mode is intended as a means to reduce system level power consumption Systems utilizing the Intel Xeon Processor 7200 Series and 7300 Series must not rely on software usage of this mechanism to limit the processor temperature ...

Page 106: ...300 Series to activate the TCC If the Thermal Monitor is enabled the TCC will be activated upon the assertion of the FORCEPR signal Assertion of the FORCEPR signal will activate TCC for all processor cores The TCC will remain active until the system deasserts FORCEPR FORCEPR is an asynchronous input FORCEPR can be used to thermally protect other system components To use the VR as an example when F...

Page 107: ...nt PECI addresses than those shown in Figure 6 7 Thermal designers should consult their third party chipset designers for the correct PECI addresses 6 3 1 1 TCONTROL and Tcc Activation on PECI Based Systems Fan speed control solutions based on PECI utilize a TCONTROL value stored in the processor IA32_TEMPERATURE_TARGET MSR This MSR uses the same offset temperature format as PECI though it contain...

Page 108: ...response rate The key items to take into account when settling on a fan control algorithm are the DTS sample rate whether the temperature filter is enabled how often the PECI host will poll the processor for temperature data and the rate at which fan speed is changed Depending on the designer s specific requirements the DTS sample rate and alpha beta filter may have no effect on the fan control al...

Page 109: ...esses Please note that each address also supports two domains Domain 0 and Domain 1 6 3 2 2 PECI Fault Handling Requirements PECI is largely a fault tolerant interface including noise immunity and error checking improvements over other comparable industry standard interfaces The PECI client is as reliable as the device that it is embedded in and thus given operating conditions that fall under the ...

Page 110: ...lid PECI transactions of GetTemp0 with a given PECI device over 3 consecutive failed transactions or a one second max specified interval then it should take appropriate actions to protect the corresponding device and or other system components from overheating The host controller may also implement an alert to software in the event of a critical or continuous fault condition 6 3 2 3 PECI GetTemp0 ...

Page 111: ...tes The Intel Xeon Processor 7200 Series and 7300 Series supports the Extended HALT state also referred to as C1E in addition to the HALT state and Stop Grant state to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 7 1 for a visual representation of the processor low power states The Extended HALT state is a lower ...

Page 112: ...em can generate a STPCLK while the processor is in the HALT state When the system deasserts STPCLK the processor will return execution to the HALT state While in HALT state the processor will process front side bus snoops and interrupts 7 2 2 2 Extended HALT State Extended HALT state is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HAL...

Page 113: ...uency and voltage operating point The processor exits the Extended HALT state when a break event occurs When the processor exits the Extended HALT state it will first transition the VID to the original value and then change the bus to core frequency ratio back to the original value Table 7 2 Extended HALT Maximum Power Symbol Parameter Min Typ Max Unit Notes PEXTENDED_HALT Quad Core Intel Xeon E73...

Page 114: ...he processor is in Stop Grant state The event will be latched and can be serviced by software upon exit from the Stop Grant state RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the de assertion of the STPCLK signal A transition to the Grant Snoop state will occur when the processo...

Page 115: ...the HALT Grant Snoop state The processor will stay in this state until the snoop on the front side bus has been serviced whether by the processor or another agent on the front side bus or the interrupt has been latched After the snoop is serviced or the interrupt is latched the processor will return to the Stop Grant state or HALT state as appropriate 7 2 4 2 Extended HALT Snoop State The Extended...

Page 116: ... frequency selection is software controlled by writing to processor MSR s Model Specific Registers thus eliminating chipset dependency If the target frequency is higher than the current frequency VCC is incremented in steps 12 5 mV by placing a new value on the VID signals and the processor shifts to the new frequency Note that the top frequency for the processor can not be exceeded If the target ...

Page 117: ... the SMBus or only support a partial implementation The Z bit is the read write bit for the serial bus transaction Note that addresses of the form 0000XXXXb are Reserved and should not be generated by an SMBus master The system designer must also ensure that their particular implementation does not add excessive capacitance to the address inputs Excess capacitance at the address inputs may cause a...

Page 118: ...nts a negative acknowledge NACK The shaded bits are transmitted by the Processor Information ROM or Scratch EEPROM and the bits that aren t shaded are transmitted by the SMBus host controller In the tables the data addresses indicate 8 bits The SMBus host controller should transmit 8 bits with the most significant bit indicating which section of the EEPROM is to be addressed the Processor Informat...

Page 119: ...bit hex digits 01 02h 16 PIROM Size Size in bytes MSB first 03h 8 Processor Data Address Byte pointer 00h if not present 04h 8 Processor Core Data Address Byte pointer 00h if not present 05h 8 L3 Cache Data Address Byte pointer 00h if not present 06h 8 Package Data Address Byte pointer 00h if not present 07h 8 Part Number Data Address Byte pointer 00h if not present 08h 8 Thermal Reference Data Ad...

Page 120: ...e 16 bit binary number in KB 29 2Ah 16 L3 Cache Size 16 bit binary number in KB 2B 2Ch 16 Maximum Cache CVID Maximum VCACHE requested by CVID outputs in mV 2D 2Eh 16 Minimum Cache Voltage Minimum processor DC VCACHE in mV 2F 30h 16 Reserved Reserved 31h 8 Checksum 1 byte checksum Package Data 32 35h 32 Package Revision Four 8 bit ASCII characters 36h 8 Reserved Reserved for future use 37h 8 Checks...

Page 121: ...sent 0 L3 Cache Present 79h 8 Processor Thread and Core Information 7 2 Number of cores 1 0 Number of threads per core 7Ah 8 Additional Processor Feature Flags 7 Reserved 6 Intel Cache Safe Technology 5 Extended Halt State C1E 4 Intel Virtualization Technology 3 Execute Disable 2 Intel 64 1 Thermal Monitor TM2 0 Enhanced Intel SpeedStep Technology 7B 7Ch 16 Thermal Adjustment Factors Pending 15 8 ...

Page 122: ... The PIROM size provides the size of the device in hex bytes The MSB is at location 01h the LSB is at location 02h 0000h 007Fh Reserved 0080h 128 byte PIROM size 0081 FFFFh Reserved Offset 03h Bit Description 7 0 Processor Data Address Byte pointer to the Processor Data section 00h Processor Data section not present 01h 0Dh Reserved 0Eh Processor Data section pointer value 0Fh FFh Reserved Offset ...

Page 123: ... effect Offset 06h Bit Description 7 0 Package Data Address Byte pointer to the Package Data section 00h Package Data section not present 01h 31h Reserved 32h Package Data section pointer value 33h FFh Reserved Offset 07h Bit Description 7 0 Part Number Data Address Byte pointer to the Part Number Data section 00h Part Number Data section not present 01h 37h Reserved 38h Part Number Data section p...

Page 124: ...um of the Header Section Writes to this register have no effect Offset 09h Bit Description 7 0 Feature Data Address Byte pointer to the Feature Data section 00h Feature Data section not present 01h 73h Reserved 74h Feature Data section pointer value 75h FFh Reserved Offset 0Ah Bit Description 7 0 Other Data Address Byte pointer to the Other Data section 00h Other Data section not present 01h 7Dh R...

Page 125: ...ading spaces 20h are programmed in this field Writes to this register have no effect Example A processor with a S Spec mark of SLA67 contains the following in field 0E 13h 20h 53h 4Ch 41h 36h 37h This data consists of one blank at 0Eh followed by the ASCII codes for SLA67 in locations 0F 13h Offset 0Eh 13h Bit Description 7 0 Character 6 S SPEC character or 20h 00h 0FFh ASCII character 15 8 Charac...

Page 126: ...ction 1 of the CPUID instruction The MSB is at location 16h the LSB is at location 19h Writes to this register have no effect Note The field is not aligned on a byte boundary since the first two bits of the offset are reserved Thus the data must be shifted left by two in order to obtain the same results Example The CPUID of a G 0 stepping Intel Xeon Processor 7200 Series and 7300 Series is 06FBh T...

Page 127: ...his register have no effect Example The Intel Xeon Processor 7200 Series and 7300 Series supports a 1066 MTS front side bus Therefore offset 1A 1Bh has a value of 042Ah Offset 16h 19h Bit Description 31 30 Reserved 00b 11b Reserved 29 21 Extended Family 00h 0Fh Extended Family 21 18 Extended Model 0h Fh Extended Model 17 16 Reserved 00b 11b Reserved 15 14 Processor Type 00b 11b Processor Type 13 1...

Page 128: ...processor Format of this field is in MHz rounded to a whole number and encoded in hex format Writes to this register have no effect Example A 2 666 GHz processor will have a value of 0A6Ah which equates to 2666 decimal 7 4 3 3 5 MAXVID Maximum Core VID This location contains the maximum Core VID Voltage Identification voltage that may be requested via the VID pins This field rounded to the next th...

Page 129: ... 7 TCASE TCASE Maximum This location provides the maximum TCASE for the processor The field reflects temperature in degrees Celsius in hex format This data can be found in Section 6 The thermal specifications are specified at the case Integrated Heat Spreader IHS Writes to this register have no effect Example A temperature of 66C would contain 42h 66 decimal in Offset 23h 7 4 3 3 8 PCDCKS Processo...

Page 130: ...n Processor 7200 Series and 7300 Series has no L3 cache Thus offset 29 2Ah will contain 0000h 0 decimal 7 4 3 4 4 MAXCVID Maximum Cache VID This location contains the maximum Cache VID Voltage Identification voltage that may be requested via the CVID pins This field rounded to the next thousandth is in mV and is reflected in hex Writes to this register have no effect Example The Intel Xeon Process...

Page 131: ...s to this register have no effect 7 4 3 5 Package Data This section provides package revision information 7 4 3 5 1 PREV Package Revision This location tracks the highest level package revision It is provided in ASCII format of four characters 8 bits x 4 characters 32 bits The package is documented as 1 0 2 0 etc If this only consumes three ASCII characters a leading space is provided in the data ...

Page 132: ...er is less than 7 characters a leading space is inserted into the value The part number should match the information found in the marking specification found in Section 3 Writes to this register have no effect Example A processor with a part number of 80565KH will have the following at offset 38 3Eh 38h 30h 35h 36h 35h 4Bh 48h Offset 32h 35h Bit Description 7 0 Character 4 ASCII character or 20h 0...

Page 133: ... this field Writes to this register have no effect Offset 38h 3Eh Bit Description 7 0 Character 7 ASCII character or 20h 00h 0FFh ASCII character 15 8 Character 6 ASCII character or 20h 00h 0FFh ASCII character 23 16 Character 5 ASCII character or 20h 00h 0FFh ASCII character 31 24 Character 4 ASCII character 00h 0FFh ASCII character 39 32 Character 3 ASCII character 00h 0FFh ASCII character 47 40...

Page 134: ...tion is reserved Writes to this register have no effect 7 4 3 7 3 TRDCKS Thermal Reference Data Checksum This location provides the checksum of the Thermal Reference Data Section Writes to this register have no effect Offset 55h 6Eh Bit Description 207 0 RESERVED 7 Offset 6F Bit Description 7 0 Part Number Data Checksum One Byte Checksum of the Part Number Section 00h FFh See Section 7 4 4 for cal...

Page 135: ...Bits are set when a feature is present and cleared when they are not Example A value of A6h can be found at offset 78h 7 4 3 8 3 Processor Thread and Core Information This location contains information regarding the number of cores and threads on the processor Writes to this register have no effect Example The Intel Xeon Processor 7200 Series and 7300 Series has two or four cores and one thread pe...

Page 136: ...on Writes to this register have no effect 7 4 3 9 Other Data These locations are reserved Writes to this register have no effect 7 4 3 9 1 FDCKS Feature Data Checksum This location provides the checksum of the Feature Data Section Writes to this register have no effect Offset 79h Bit Description 7 2 Number of cores 1 0 Number of threads per core Offset 7Ah Bit Description 7 Reserved 6 Intel Cache ...

Page 137: ... be used for other data at the system or processor vendor s discretion The data in this EEPROM once programmed can be write protected by asserting the active high SM_WP signal This signal has a weak pull down 10 kΩ to allow the EEPROM to be programmed in systems with no implementation of this signal The Scratch EEPROM resides in the upper half of the memory component addresses 80 FFh The lower hal...

Page 138: ...Features 138 Document Number 318080 002 ...

Page 139: ... a cooling solution Future revisions may have solutions that differ from those discussed here 8 2 Thermal Specifications Please see Chapter 6 for the the cooling requirements of the boxed processor 8 2 1 Boxed Processor Cooling Requirements A suitable heatsink is required to properly cool the boxed processor However meeting the processor s temperature specifications is also a function of the therm...

Page 140: ...Boxed Processor Specifications 140 Document Number 318080 002 ...

Page 141: ... 7200 Series and 7300 Series systems Tektronix and Agilent should be contacted to obtain specific information about their logic analyzer interfaces The following information is general in nature Specific information must be obtained from the logic analyzer vendor Due to the complexity of Intel Xeon Processor 7200 Series and 7300 Series based multiprocessor systems the LAI is critical in providing ...

Page 142: ...al performance of the FSB therefore it is critical to obtain electrical load models from each of the logic analyzer vendors to be able to run system level simulations to prove that their tool will work in the system Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide ...

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