Embedded Intel® Atom™ Processor N2800 with Intel® NM10 Express Chipset Development Kit User‘s Manual
96
Table 51. Port 80h POST Codes
(continued)
Port 80 Code
Progress Code Enumeration
CPU DXE SMM Phase
0x4D
CPU DXE SMM Phase begin
0x4E
Relocate SM bases for all APs
0x4F
CPU DXE SMM Phase end
I/O BUSES
0x50
Enumerating PCI buses
0x51
Allocating resources to PCI bus
0x52
Hot Plug PCI controller initialization
USB
0x58
Resetting USB bus
0x59
Reserved for USB
ATA/ATAPI/SATA
0x5A
Resetting PATA/SATA bus and all devices
0x5B
Reserved for ATA
BDS
0x60
BDS driver entry point initialize
0x61
BDS service routine entry point (can be called multiple times)
0x62
BDS Step2
0x63
BDS Step3
0x64
BDS Step4
0x65
BDS Step5
0x66
BDS Step6
0x67
BDS Step7
0x68
BDS Step8
0x69
BDS Step9
0x6A
BDS Step10
0x6B
BDS Step11
0x6C
BDS Step12
0x6D
BDS Step13
0x6E
BDS Step14
0x6F
BDS return to DXE core (should not get here)
Keyboard (PS/2 or USB)
0x90
Resetting keyboard
0x91
Disabling the keyboard
0x92
Detecting the presence of the keyboard
0x93
Enabling the keyboard
0x94
Clearing keyboard input buffer
0x95
Instructing keyboard controller to run Self Test (PS/2 only)
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