82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide
22
Application Note (AP-468)
3.6.10
82541PI(ER) Oscillator Solution
There are two oscillator solutions for the 82541PI(ER): high voltage and low voltage.
3.6.10.1
High Voltage Solution (VDD = 3.3 V)
This solution involves capacitor C1, which forms a capacitor divider with C
stray
of about 20 pF.
This attenuates the input clock amplitude and adjusts the clock oscillator load capacitance.
V
in
= VDD * (C1/(C1 + C
stray
))
V
in
= 3.3 * (C1/(C1 + C
stray
))
This enables load clock oscillators of 15 pF to be used. If the value of C
stray
is unknown, C1 should
be adjusted by tuning the input clock amplitude to approximately 1 V
ptp
. If C
stray
equals 20 pF,
then C1 is 10 pF ±10%.
A low capacitance, high impedance probe (C < 1 pF, R > 500 K
Ω
) should be used for testing.
Probing the parameters can affect the measurement of the clock amplitude and cause errors in the
adjustment. A test should also be done after the probe has been removed for circuit operation.
If jitter performance is poor, a lower jitter clock oscillator can be implemented.
Table 16. 82541PI Clock Oscillator Specifications
Symbol
Parameter
Specifications
Units
Min
Typical
Max
f0
Frequency
25
MHz
df0
Frequency Variation
-50
+30
ppm
Dc
Duty Cycle
40
60
%
tr
Rise Time
5
ns
tf
Fall Time
5
ns
σ
i
Clock Jitter, rms (if specified)
50
ps
C1
Clock Capacitance (pushed by clock)
15
50
pF
VDD
Supply Voltage
3.3 or 1.8
V
Operating
temperature
70
° C
CMOS output
levels
Voltage Output High (Voh),
Voltage Output Low (Vol)
80% VDD
20% VDD
V
V
X1
K14
Clk oscillator
VDD=3.3
C1~10pF
Tabor
Cstray~20pF
Board Capacitance
Not a Component
82541PI(ER)
