82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide
18
Application Note (AP-468)
3.6.5
82541PI(ER) Controller Test Capability
The 82541PI(ER) controller contains a test access port conforming to the IEEE 1149.1a-1994
(JTAG) Boundary Scan specification. To use the test access port, these balls need to be connected
to pads accessible by the test equipment. The TRST# input also needs to be connected to ground
through a pull-down resistor (approximately 100
Ω
) so that the test capability cannot be invoked by
mistake.
A Boundary Scan Definition Language (BSDL) file describing the 82541PI(ER) controller is
available for use in your test environment.
The 82541PI(ER) controller also contains an XOR test tree mechanism for simple board tests.
Details of XOR tree operation may be obtained through your Intel representative.
3.6.6
Serial EEPROM for 82541PI(ER) Controller Implementations
82541PI(ER) controllers can use either a Microwire* or an SPI* serial EEPROM. The EEPROM
mode is selected on the EEMODE input (pin J4). A no connect denotes an SPI EEPROM and a
pull-down resistor to ground denotes a Microwire EEPROM. Several words of the EEPROM are
accessed automatically by the device after reset to provide pre-boot configuration data before it is
accessed by host software. The remainder of the EEPROM space is available to software for
storing the MAC address, serial numbers, and additional information.
For non-ASF applications, a 64 register by 16-bit Microwire serial EEPROM should be used, and
for ASF 1.0 applications, a larger 93C66 Microwire or AT25040 SPI* serial EEPROM. ASF 2.0
requires an 8 KB SPI* serial EEPROM.
Intel has an MS-DOS* software utility called EEUPDATE, which can be used to program
EEPROM images in development or production line environments. To obtain a copy of this
program, contact your Intel representative.
The EEPROM access algorithm programmed into the 82541PI(ER) controller is compatible with
most, but not all, commercially available 3.3 V Microwire* interface, serial EEPROM devices,
with 64 x 16 (or 256 x 16) organization and a 1 MHz speed rating. The 82541PI(ER) EEPROM
access algorithm drives extra pulses on the shift clock at the beginnings and ends of read and write
cycles. The extra pulses may violate the timing specifications of some EEPROM devices. In
selecting a serial EEPROM, choose a device that specifies “don't care” shift clock states between
accesses.
Microwire EEPROMs that have been found to work satisfactorily with the 82541PI(ER) Gigabit
Ethernet controller are listed in
Table 10. Microwire 64 x 16 Serial EEPROMs
Manufacturer
Manufacturer's Part Number
Atmel
AT93C46
1
Catalyst
CAT93C46
1,2
1.
No manageability provided.
2.
Revision H is not supported. Product die revision letter is marked on top of the package as a suffix to the production data
code (e.g., AYWW
H
.)
