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82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide

Application Note (AP-468)

15

3.4.5

Magnetics Modules for 82562GZ(GX) PLC Devices

A 5-core magnetics module should be carefully selected for specific designs.

lists

suggested integrated magnetics modules for use with 82562GZ(GX) PLC devices. These modules
also contain integrated USB jacks.

Note:

These components are pin-compatible with the magnetics modules listed in

for the

82541PI(ER) controller.

3.5

Flash Interface

The ICHx does not support a Flash interface.

Note:

The Intel Boot Agent is supported via the System BIOS.

3.6

Designing with 82541PI(ER) Gigabit Controllers

This section provides design guidelines specific to 82541PI(ER) Gigabit Ethernet Controllers.

3.6.1

82541PI(ER) Gigabit Controller LAN Disable Guidelines

The 82541PI(ER) controller has a LAN disable function that is present on FLSH_SO, ball P9. This
pin can be connected to a Super IO component to allow the BIOS to disable the Ethernet port (see

). If the serial Flash interface is populated, the Flash serial output pin must not interfere

with this function.

Do not attempt to use the LAN_POWER_GOOD signal for a LAN disable input on the
82541PI(ER) controller. This pin is intended to operate as a power-on reset connected to a power
monitor circuit.

The input of the 82541PI(ER) FLSH_SO (pin P9) is the LAN_DISABLE# signal. It is sampled on
the rising edge of LAN_PWR_GOOD or RST#. The signal must be held valid for 80 ns after either
rising edge.

If it is sampled high, the LAN functions normally. If it is sampled low, then the following occurs:

1. The LAN is disabled.

2. The PHY is powered down.

Table 9. Recommended Magnetics Modules

Manufacturer

Part Number

Type

Pulse

H1138

Discrete

Pulse

JWOA1P01R

Integrated

Stewart Connector
Systems

SI-70027

RJ-45/Magnetic

Pulse

H1338 (MDI-X only)

Discrete

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Summary of Contents for 82541PI

Page 1: ...82541PI ER and 82562GZ GX Dual Footprint LOM Design Guide Application Note AP 468 Revision 2 1 April 2005...

Page 2: ...t not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for con...

Page 3: ...e schematics Added Appendix A Measuring LAN Reference Frequency Using a Fre quency Counter 1 3 Dec 2004 Removed confidential status Added reference schematics 2 0 Feb 2005 Added 82541PI ER board desig...

Page 4: ...iv Application Note AP 468 82541PI ER and 82562GZ GX Dual Footprint LOM Design Guide Note This page is intentionally left blank...

Page 5: ...eramic Resonator 6 3 0 Ethernet Component Design Guidelines 7 3 1 General Design Considerations for Ethernet Controllers 7 3 1 1 Crystal Selection Parameters 7 3 1 2 Reference Crystal 11 3 1 3 Referen...

Page 6: ...gnetics to RJ45 Priority 1 27 4 2 2 Distance B PHY to Magnetics Priority 2 28 4 2 3 Distance C LAN Controller to Chipset Priority 3 28 4 2 4 Distance D The Overall Length of Differential Traces from L...

Page 7: ...ment Distances 26 5 Critical Dimensions for Component Placement Discrete Magnetics Solution 27 6 Critical Dimensions for 82562GZ GX and 82541PI ER Component Placement with Integrated Magnetics Module...

Page 8: ...M 14 8 Recommended EEPROM Manufacturers 14 9 Recommended Magnetics Modules 15 10 Microwire 64 x 16 Serial EEPROMs 18 11 SPI Serial EEPROMs for 82541PI ER Controller 19 12 82541PI ER EEPROM Memory Layo...

Page 9: ...mber and pattern of pins and layout of signals that allow for the flexible cost effective multipurpose design Therefore it is easy to populate a single board design with any of the two parts to maximi...

Page 10: ...es Table 1 lists the product ordering codes for the 82541PI ER and the 82562GZ GX 1 5 82541PI ER Gigabit Ethernet Controllers Intel 82541PI ER Gigabit Ethernet controllers are single compact component...

Page 11: ...or 82562GZ GX devices 1 6 1 1 Mode 0 Drop in Replacement Mode 0 is a drop in replacement for a similar 82562EZ EX device without any required software or hardware modifications 82562EZ EX product coll...

Page 12: ...circuit design Mode 2 Same as mode 1 except LED configuration C Usability and reduced BOM cost Strapping resistors LAN Disable circuit and LED circuit design Mode 3 LED configuration B Single Pin LAN...

Page 13: ...also have bus clock input functionality however a discussion of this feature is beyond the scope of this document and will not be addressed The chosen frequency control device vendor should be consult...

Page 14: ...or The frequency multipliers and divisors are controlled by programmable fuses A programmable oscillator s accuracy depends heavily on the Ethernet controller s differential transmit lines The Physica...

Page 15: ...rally considered to be the mainstay of frequency control components due to their low cost and ease of implementation They are available from numerous vendors in many package types and with various spe...

Page 16: ...fundamental mode crystals Third overtone crystals are more suitable for use in military or harsh industrial environments Third overtone crystals require a trap circuit extra capacitor and inductor in...

Page 17: ...ode The terms series resonant and parallel resonant are often used to describe crystal circuits Specifying parallel mode is critical to determining how the crystal frequency is calibrated at the facto...

Page 18: ...e actual load will pull the oscillator slightly off frequency Note C1 and C2 can vary by as much as 5 approximately 1 pF from their nominal values 3 1 1 7 Shunt Capacitance The shunt capacitance param...

Page 19: ...stal to use in subsequent frequency tests to determine the best values for C1 and C2 If a crystal analyzer is not available then the selection of a reference crystal can be done by measuring a statist...

Page 20: ...used while performing the frequency measurements to select the appropriate value for C1 and C2 3 1 5 Temperature Changes Temperature changes can cause the crystal frequency to shift Therefore frequenc...

Page 21: ...ting the published specifications 3 Perform physical layer conformance testing and EMC FCC and EN testing in real systems Note Magnetics modules for 1000Base T Ethernet are similar to those designed s...

Page 22: ...Information Note See your Intel representative for later information on later versions of the I O Control Hub Note No manageability provided Note Legacy manageability only Table 6 82562GZ GX Memory L...

Page 23: ...roller has a LAN disable function that is present on FLSH_SO ball P9 This pin can be connected to a Super IO component to allow the BIOS to disable the Ethernet port see Figure 3 If the serial Flash i...

Page 24: ...V supply must provide approximately 500 mA current and the 1 8 V supply approximately 230 mA current The 3 3 V supply must provide only 30 mA current A central power supply can provide all the requir...

Page 25: ...s placing them as close to the device power connections as possible 3 6 4 82541PI ER Controller Power Management and Wake Up The 82541PI ER controller supports low power operation as defined in the PC...

Page 26: ...s available to software for storing the MAC address serial numbers and additional information For non ASF applications a 64 register by 16 bit Microwire serial EEPROM should be used and for ASF 1 0 ap...

Page 27: ...ested integrated magnetics modules for use with the 82541PI ER controller These modules also contain integrated USB jacks A good quality Gigabit Ethernet magnetics module can also be used with the 825...

Page 28: ...1 through 100 MHz 43 dB minimum 100 1 through 150 MHz 42 dB minimum Effective Common Mode to Common Mode Reject 1 0 through 60 MHz 38 dB minimum 60 1 through 100 MHz 34 dB minimum 100 1 through 150 MH...

Page 29: ...cillator can impact the 82541PI clock and its performance Table 15 Electrical Specifications at 25 C for 1000 Gb Silicon Insertion Loss TX RX 0 1 through 999 kHz 1 0 dB maximum 1 0 through 60 0 MHz 0...

Page 30: ...low capacitance high impedance probe C 1 pF R 500 K should be used for testing Probing the parameters can affect the measurement of the clock amplitude and cause errors in the adjustment A test shoul...

Page 31: ...ncludes a low consumption and low jitter clock oscillator that uses a 1 8 V external power supply In this case C1 will require adjusting according to the stray capacitance from X1 Table 17 82541PI ER...

Page 32: ...82541PI ER and 82562GZ GX Dual Footprint LOM Design Guide 24 Application Note AP 468 Note This page intentionally left blank...

Page 33: ...ssions and component operating temperature This section provides guidelines for component placement Careful component placement can Decrease potential problems directly related to EMI which could caus...

Page 34: ...ther potentially noisy traces away from the crystal traces The restraining straps of the crystal should be grounded to reduce the possibility of radiation from the crystal s case Crystals should lay f...

Page 35: ...the RJ45 connector should be kept to less than one inch of separation The following trace characteristics are important and should be observed Differential Impedance The differential impedance should...

Page 36: ...red that the system meets specified timings This can be verified through simulations or other techniques The LCI can be routed to support a 10 100 Mbps LOM solution with 82562GZ GX devices Distance C...

Page 37: ...ce 4 3 2 Distance B Ethernet Controller to Chipset For LCI on 82562GZ GX devices the maximum length should be less than 10 inches on an ICH5 ICH6 or ICH7 platform For the PCI bus on 82541PI ER control...

Page 38: ...rs For the 82541PI ER keep at least 5 times the distance to the reference plane between all four Tx and Rx differential pairs For all Ethernet controllers do not route any other signal traces parallel...

Page 39: ...er 1 that is 8 mils 0 2 mm wide and 2 mils 0 05 mm thick with a spacing of eight mils 0 2mm If the fiberglass layer is 8 mils 0 2 mm thick with a dielectric constant ER of 4 7 the calculated single en...

Page 40: ...d to every ground plane layer similarly every power via should be connected to all equal potential power plane layers This helps reduce circuit inductance Another recommendation is to physically locat...

Page 41: ...s from analog grounds to reduce coupling Noisy digital grounds can affect sensitive DC subsystems All ground vias should be connected to every ground plane layer similarly every power via should be co...

Page 42: ...of magnetics module Figure 8 illustrates the split plane layout for a discrete magnetics module Capacitors are used to interconnect chassis ground and signal ground Figure 8 Ground Plane Separation F...

Page 43: ...egrated USB ports on the magnetics module might have difficulty using a chassis ground configuration due to the need to get DC ground to certain USB pins One technique is to fabricate an incomplete gr...

Page 44: ...the magnetics module to ground Depending on overall shielding and grounding design this may be done to the chassis ground signal ground or a termination plane Care must be taken when using various gro...

Page 45: ...lacing a decoupling cap on the power trace once every few inches greatly reduces the amount of noise that will reach the LAN device In turn this reduces radiated emissions and improves IEEE PHY confor...

Page 46: ...ation For 100Base TX designs the IEEE specification allows a 950 mVpk to 1050 mVpk for the negative peak and 950 mVpk to 1050 mVpk for the positive peak Ideally a typical PCB output amplitude should b...

Page 47: ...duce the amount of crosstalk on the differential pairs TDP and TDN and RDP and RDN from the unused pairs of the RJ45 Pads may be placed for additional capacitance which may be required if failure occu...

Page 48: ...onents such that the length and symmetry of the differential pairs are not disturbed 4 8 Light Emitting Diodes for Designs Based on 82541PI ER The 82541PI ER controller provides four programmable high...

Page 49: ...hoosing the pin compatible magnetics modules for both 10 100 and gigabit controller 2 Terminating unused differential signals for gigabit between the selected magnetics module and RJ 45 connector when...

Page 50: ...Figure 16 Typical Magnetics for Gigabit LAN Controller with Optional Resistors Footprint ADP ADN ADCT AXP AXN AXCT RXN RXCT RDP RDN RDCT RXP TDP TDN TDCT TXP TXN TXCT RXN RXCT RDP RDN RDCT RXP Pin_2 P...

Page 51: ...ches is to rework the magnetics module for gigabit controller with internal jumpers to short pair three and four of differential signals OEMs need to work with their magnetics vendors for this option...

Page 52: ...for 10 100 LOM Design 4 10 3 Option 3 Integrated Magnetics Module for 10 100 Mbps and Gigabit Refer to Table 13 Pin_2 Pin_1 Pin_3 Pin_6 Pin_7 Pin_8 Pin_5 Pin_4 LAN Connector Rz Rw Rx Ry ADP ADN ADCT A...

Page 53: ...test is a good indicator of real world network performance It should be done with long and short cables and many link partners The test limit is 10 to 11 errors 10 100 1000 Mbps 2 Output Amplitude Ris...

Page 54: ...ntroller the trace pairs should be kept 0 1 inch or more away from the other trace pairs The only possible exceptions are in the vicinities where the traces enter or exit the magnetics the RJ 45 conne...

Page 55: ...NC A2 SERR SERR NC SERR SERR No stuff A3 VCC 3 3 V VCC 3 3 V 3 3 V A4 IDSEL IDSEL NC IDSEL IDSEL No stuff A5 AD 25 AD 25 NC AD 25 AD 25 No stuff A6 NC PME NC No stuff PME No stuff A7 VCC 3 3 V VCC 3...

Page 56: ...stuff C5 NC RSVD_NC NC NC C6 AD 28 AD 28 NC AD 28 AD28 No stuff C7 AD 29 AD 29 NC AD 29 AD29 No stuff C8 NC CLK_RUN NC NC CLK_RUN No stuff C9 VCC SMBDATA NC 3 3 V SMBDATA C10 VSS VSS VSS C11 ACTIVITY...

Page 57: ...o this signal for 82562GZ GX Has an internal 10 K pull down resistor for the 82562GZ GX E1 VCC 3 3 V VCC 3 3 V 3 3 V E2 VSS VSS VSS E3 AD 17 AD 17 NC AD 17 AD 17 No stuff E4 VSS RSVD_VSS VSS E5 VSS VS...

Page 58: ...CR 1 2 V 1 2 V 3 3 V Core Power Plane G6 1 2 V 1 2 V VCC 1 2 V 1 2 V 3 3 V Core Power Plane G7 VSS VSS VSS G8 VSS VSS VSS G9 VSS VSS VSS G10 VSS VSS VSS G11 AVSS AVSS VSS VSS VSS VSS AVSS VSS G12 ANAL...

Page 59: ...for Microwire and a NC for SPI J5 1 2 V 1 2 V VCCR 1 2 V 1 2 V 3 3 V Core Power Plane J6 1 2 V 1 2 V 3 3 V 1 2 V 1 2 V 3 3 V Core Power Plane J7 1 2 V 1 2 V 3 3 V 1 2 V 1 2 V 3 3 V Core Power Plane J8...

Page 60: ...1 2 V 1 2 V 3 3 V 1 2 V 1 2 V 3 3 V Core Power Plane L6 VSS VSS VSS VSS L7 NC RSVD_NC ADV10 LAN_DISABLE NC NC NC An internal 10 K pull down resistor is required for the 82562GZ GX L8 NC NC NC NC 1 8 V...

Page 61: ...VSS VSS VSS VSSPP VSS N2 AD 10 AD 10 NC AD 10 AD 10 No stuff N3 AD 9 AD 9 NC AD 9 A D9 No stuff N4 AD 7 AD 7 NC AD 7 AD 7 No stuff N5 AD 4 AD 4 NC AD 4 AD 4 No stuff N6 VCC 3 3 V VCC 3 3 V 3 3 V 3 3 V...

Page 62: ...ignal P10 EEDI EEDI NC EEDI EEDI EEDI If desired this can be shorted to the ICH EEDI because it is an input in ICH in reset P11 CTRL12 CTRL12 NC Pwr Regulator Pwr Regulator No stuff Connect to PNP Don...

Page 63: ...int LOM Design Guide Application Note AP 468 55 6 0 Self Review Checklist for Combined Footprint LOM A Portable Data Format PDF Self Review Checklist for a Combined Footprint LOM is available to aid d...

Page 64: ...82541PI ER and 82562GZ GX Dual Footprint LOM Design Guide 56 Application Note AP 468 Note This page intentionally left blank...

Page 65: ...82541PI ER and 82562GZ GX Dual Footprint LOM Design Guide Application Note AP 468 57 7 0 Reference Schematics Following are reference schematics for the 82541PI ER and 82562GX EX Mode 0 and 1...

Page 66: ...J L V H H F Q H U H I H 5 5 3 5HI HVLJQ P P P P K F W L S P P H DQG DUH LQWHUFKDQJDEOH W R 1 5 3 J Q L V X I L W Q H Q R S P R F O O D W V Q J Q L V X I L W Q H Q R S P R F O O D W V Q G H O O D W V Q...

Page 67: ...V H W N F R O F H U L Z R U F L 0 J Q L V X I L O O D W V Q V H F L Y H G 0 2 5 3 O R F R W R U S 3 6 J Q L V X I L O O D W V Q L W R Q R V H F L Y H G 0 2 5 3 0 6 G Q D 0 6 H K W W D K W H U X V Q K...

Page 68: ...R U F D Z R O H E G H W D F R O H U D W L O S V 1 R W H F D O 3 H O X G R P V F L W H Q J D P H K W H K W R W H O E L V V R S V D H V R O F V D H O X G R P V F L W H Q J D P U D H Q V U R W L F D S D...

Page 69: ...D F O L D U U H Z R S 9 9 V S D F O L D U U H Z R S H U R F 9 9 H O E L V V R S V D H V R O F V D G H F D O S H E G O X R K V H F L Y H G V L K 7 W H Q U H K W H K W I R V Q L S W X S Q L O D W V U F...

Page 70: ...U V W Q H Q R S P R F H V H K W H F D O 3 U H O O R U W Q R 1 H K W R W H V R O F 7 9 7 7 9 7 5 7 1 1 V S E 0 N Q L I I 2 V S E 0 N Q L Q H H U V S E 0 N Q L Z R O O H U R W F H Q Q R F I R V S D W U...

Page 71: ...R 1 U R 5 3 Q J L V H H F Q H U H I H 5 P P P P K F W L S P P H DQG DUH LQWHUFKDQJDEOH W R 1 5 3 J Q L V X I L W Q H Q R S P R F O O D W V Q J Q L V X I L W Q H Q R S P R F O O D W V Q G H O O D W V Q...

Page 72: ...G 0 2 5 3 O R F R W R U S 3 6 J Q L V X I L O O D W V Q L W R Q R V H F L Y H G 0 2 5 3 P K 2 1 2 3 P K 2 N 5 K W L Z U R W V L V H U P K R O O D W V Q 5 U R 5 3 J Q L V X Q H K Z U R W V L V H U R Q...

Page 73: ...U D W L O S V 1 R W H F D O 3 H O X G R P V F L W H Q J D P H K W H K W R W H O E L V V R S V D H V R O F V D H O X G R P V F L W H Q J D P V U R W L F D S D F H H U K W H V H K 7 1 B 6 6 6 H K W V V...

Page 74: ...O O R U W Q R 5 3 J Q L V X Q H K Z G H U L X T H U U H Z R S Y U H O O R U W Q R 5 3 J Q L V X 3 6 5 2 2 6 7 9 7 1 6 6 5 2 7 8 5 7 1 5 7 7 6 5 6 1 3 3 5 7 6 1 6 3 5 5 2 3 H O E L V V R S V D H V R O...

Page 75: ...H 7 9 7 5 7 1 1 7 9 7 V W Q H Q R S P R F H V H K W H F D O 3 U H O O R U W Q R 1 H K W R W H V R O F 3 8 1 Q H H U 1 5 3 3 2 V H V R S U X S J Q L W V H W U R J X E H G O D L F H S V U R I O Q R O O...

Page 76: ...82541PI ER and 82562GZ GX Dual Footprint LOM Design Guide 68 Application Note AP 468 Note This page intentionally left blank...

Page 77: ...e used to measure the transmitter reference frequency or transmitter reference clock If the transmitter reference frequency is more than 20 ppm below the target frequency then the values for C1 and C2...

Page 78: ...d for indirect probing of the transmitter reference clock The buffered 125 MHz clock will be a 5X multiple of the crystal circuit s reference frequency Figure 19 Different LAN devices may require diff...

Page 79: ...the 125 MHz buffered reference clock 5 Determine the center reference frequency as accurately as possible This can be done by taking 30 to 50 different readings using the frequency counter and then ca...

Page 80: ...ence frequency is more than 8 ppm above the target frequency then the values for C1 and C2 are too small and they should be increased When tests are performed across temperature it may be acceptable f...

Page 81: ...controls for your model of high resolution digital counter make sure it can display 25 0000 MHz with at least four decimal places frequency resolution 4 Ensure the LAN circuits are powered 5 Determine...

Page 82: ...re than 8 ppm below the target frequency then the values for C1 and C2 are too big and they should be decreased When tests are performed across temperature it may be acceptable for the center frequenc...

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