82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide
16
Application Note (AP-468)
3. Most MAC clock domains are gated.
4. Most functional blocks are held in reset.
5. PCI inputs and outputs are floated.
6. The device will not respond to PCI cycles (including configuration cycles).
7. The device is put in a low power state, which is equivalent to D3 without wakeup or
manageability.
Note:
To use this configuration for the 82562GZ(GX) PLC device, be sure the AND gate U1 is
populated. Depopulate the 0
Ω
resistor R2.
Figure 3. 82541PI(ER) LAN Disable Circuitry
3.6.2
Power Supplies for 82541PI(ER) Gigabit Ethernet Controllers
The 82541PI(ER) controller requires three power supplies: 1.2 V, 1.8 V, and 3.3 V. The 1.2 V
supply must provide approximately 500 mA current, and the 1.8 V supply, approximately 230 mA
current. The 3.3 V supply must provide only 30 mA current.
A central power supply can provide all the required voltage sources, or the power can be derived
and regulated locally near the Ethernet control circuitry. All voltage sources must remain present
during power down in order to use the 82541PI(ER) LAN wake up capability. This consideration
makes it more likely that at least some of the voltage sources will be local.
Instead of using external regulators to supply 1.2 V and 1.8 V, power transistors can be used in
conjunction with on-chip regulation circuitry. (See the reference schematic for an implementation
example.)
IO
Control
Hub 5, 6,
or 7
Super IO
Chip
82541PI(ER)
RST#
RST# (B9)
RSM_RST#
R1
10 K
R2
0 Ohm
Pop = Y
LAN_PWR_GOOD
(A9)
82562GZ(GX) Disable Circuit
U1
FLSH_SO
(P9)
Pop = Y means populate this option
