Specification Update
29
BJ45.
Clock Modulation Duty Cycle Cannot be Programmed to 6.25%
Problem:
When programming field T_STATE_REQ of the IA32_CLOCK_MODULATION MSR (19AH)
bits [3:0] to '0001, the actual clock modulation duty cycle will be 12.5% instead of the
expected 6.25% ratio.
Implication:
Due to this erratum, it is not possible to program the clock modulation to a 6.25% duty
cycle.
Workaround:
None identified
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ46.
Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value
for VEX.vvvv May Produce a #NM Exception
Problem:
The VAESIMC and VAESKEYGENASSIST instructions should produce a #UD (Invalid-
Opcode) exception if the value of the vvvv field in the VEX prefix is not 1111b. Due to
this erratum, if CR0.TS is “1”, the processor may instead produce a #NM (Device-Not-
Available) exception.
Implication:
Due to this erratum, some undefined instruction encodings may produce a #NM instead
of a #UD exception.
Workaround:
Software should always set the vvvv field of the VEX prefix to 1111b for instances of
the VAESIMC and VAESKEYGENASSIST instructions
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ47.
Memory Aliasing of Code Pages May Cause Unpredictable System
Behavior
Problem:
The type of memory aliasing contributing to this erratum is the case where two
different logical processors have the same code page mapped with two different
memory types. Specifically, if one code page is mapped by one logical processor as
write-back and by another as uncachable and certain instruction fetch timing conditions
occur, the system may experience unpredictable behavior.
Implication:
If this erratum occurs the system may have unpredictable behavior including a system
hang. The aliasing of memory regions, a condition necessary for this erratum to occur,
is documented as being unsupported in the Intel 64 and IA-32 Intel® Architecture
Software Developer's Manual, Volume 3A, in the section titled Programming the PAT.
Intel has not observed this erratum with any commercially available software or
system.
Workaround:
Code pages should not be mapped with uncacheable and cacheable memory types at
the same time.
Status:
For the steppings affected, see the Summary Tables of Changes.
