Specification Update
25
BJ33.
Unsupported PCIe Upstream Access May Complete with an Incorrect
Byte Count
Problem:
PCIe Upstream IO and Configuration accesses are not supported. If an IO or
Configuration request is received upstream, the integrated PCIe controller will treat it
as an unsupported request, the request will be dropped, and a completion will be sent
with the UR (Unsupported Request) completion status. This completion, according to
the PCIe specification, should indicate a byte count of 4. Due to this erratum, the byte
count is set to the same byte count as the offending request.
Implication:
The processor response to an unsupported PCIe access may not fully comply to the
PCIe specification.
Workaround:
PCIe agents should not issue unsupported accesses.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ34.
Malformed PCIe Transactions May be Treated as Unsupported
Requests Instead of as Critical Errors
Problem:
PCIe MSG/MSG_D TLPs (Transaction Layer Packets) with incorrect Routing Code as well
as the deprecated TCfgRD and TCfgWr types should be treated as malformed
transactions leading to a critical error. Due to this erratum, the integrated PCIe
controller's root ports may treat such messages as UR (Unsupported Requests).
Implication:
Legacy malformed PCIe transactions may be treated as UR instead of as critical errors.
Workaround:
None identified
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ35.
PCIe Root Port May Not Initiate Link Speed Change
Problem:
PCIe specification rev 2.0 requires the upstream component to maintain the PCIe link
at the target link speed or the highest speed supported by both components on the
link, whichever is lower. PCIe root port will not initiate the link speed change without
being triggered by the software. System BIOS will trigger the link speed change under
normal boot scenarios. However, BIOS is not involved in some scenarios such as link
disable/re-enable or secondary bus reset and therefore the speed change may not
occur unless initiated by the downstream component. This erratum does not affect the
ability of the downstream component to initiate a link speed change. All known 5.0Gb/
s-capable PCIe downstream components have been observed to initiate the link speed
change without relying on the root port to do so.
Implication:
Due to this erratum, the PCIe root port may not initiate a link speed change during
some hardware scenarios causing the PCIe link to operate at a lower than expected
speed. Intel has not observed this erratum with any commercially available platform.
Workaround:
None identified
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ36.
Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR or
XSAVE/XRSTOR Image Leads to Partial Memory Update
Problem:
A partial memory state save of the FXSAVE or XSAVE image or a partial memory state
restore of the FXRSTOR or XRSTOR image may occur if a memory address exceeds the
64KB limit while the processor is operating in 16-bit mode or if a memory address
exceeds the 4GB limit while the processor is operating in 32-bit mode.
Implication:
FXSAVE/FXRSTOR or XSAVE/XRSTOR will incur a #GP fault due to the memory limit
violation as expected but the memory state may be only partially saved or restored.
