Motorola M68MPB916X1 User Manual Download Page 1

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M68MPB916X1UM/D

October 1998

M68MPB916X1

MCU PERSONALITY BOARD

USER’S MANUAL

Summary of Contents for M68MPB916X1

Page 2: ... the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of direct...

Page 3: ...2 5 2 2 3 Voltage Reference High Select Header W3 2 6 2 2 4 Voltage Reference Low Select Header W4 2 7 2 2 5 VSSA Insertion Point E1 2 7 2 3 ANALOG DIGITAL CIRCUITS 2 8 2 4 MEVB CONFIGURATION 2 9 2 5 ACTIVE PROBE CONFIGURATION 2 11 CHAPTER 3 MEVB QUICK START GUIDE 3 1 INTRODUCTION 3 1 3 2 CONFIGURING THE MPFB 3 1 3 2 1 MPFB Memory Devices 3 1 3 2 2 MPFB Jumper Headers 3 2 3 3 MEVB INSTALLATION INS...

Page 4: ... MAPI Interface Connector Layout 5 1 5 2 MAPI Interface Connector P1 Pin Assignments 5 2 5 3 MAPI Interface Connector P2 Pin Assignments 5 3 5 4 MAPI Interface Connector P3 Pin Assignments 5 4 5 5 MAPI Interface Connector P4 Pin Assignments 5 5 TABLES 1 1 MPB Specifications 1 2 2 1 Jumper Header Types 2 3 2 2 MPB Jumper Header Descriptions 2 3 3 1 MPFB Quick Start Jumper Header Configuration 3 2 4...

Page 5: ...lyzer Connector J14 Pin Assignments 4 8 4 9 Logic Analyzer Connector J15 Pin Assignments 4 8 4 10 Logic Analyzer Connector J16 Pin Assignments 4 9 4 11 Logic Analyzer Connector J17 Pin Assignments 4 9 4 12 Logic Analyzer Connector J18 Pin Assignments 4 10 4 13 Logic Analyzer Connector J19 Pin Assignments 4 10 4 14 Logic Analyzer Connector J20 Pin Assignments 4 11 ...

Page 6: ...CONTENTS vi M68MPB916X1UM D ...

Page 7: ...e MEVB consists of the M68MPFB1632 Modular Platform Board MPFB and an MPB Alternately you may install the MPB directly in your target system if the target system includes a modular active probe interconnect MAPI interface The MCU device on the MPB defines which MCU is emulated evaluated by the MMDS or evaluated by the MEVB Both systems are invaluable tools for designing debugging and evaluating MC...

Page 8: ... non condensing Power requirements 5 Vdc 5 500 mA max Dimensions Size Weight 3 25 x 3 25 in 82 6 x 82 6 mm 2 9 oz 82 2 grams 1 3 EQUIPMENT REQUIRED The external requirements for MPB operation are either an MPFB or MMDS system For MMDS operation requirements see the MMDS1632 Motorola Modular Development System User s Manual MMDS1632UM D For operation requirements for the MEVB see this manual and th...

Page 9: ...52 6106888 Tai Po 852 6668333 INDIA Bangalore 91 80 5598615 ISRAEL Herzlia 972 9 590222 ITALY Milan 39 2 82201 JAPAN Fukuoka 81 92 725 7583 Gotanda 81 3 5487 8311 Nagoya 81 52 232 3500 Osaka 81 6 305 1802 Sendai 81 22 268 4333 Takamatsu 81 878 37 9972 Tokyo 81 3 3440 3311 KOREA Pusan 82 51 4635 035 Seoul 82 2 554 5118 MALAYSIA Penang 60 4 2282514 MEXICO Mexico City 52 5 282 0230 Guadalajara 52 36 ...

Page 10: ...GENERAL INFORMATION 1 4 M68MPB916X1UM D ...

Page 11: ...PB installation in the MMDS and MEVB The MPB has been factory tested and is shipped with installed jumpers A jumper installed on a jumper header provides a connection between two points in the MPB circuit The MPB has two types of jumper headers three pin and two pin with a cut trace short A cut trace short has a copper trace between the feed through holes bottom or solder side of the MPB Table 2 1...

Page 12: ...W2 wiring trace short cut trace short Be careful not to cut adjacent PCB traces nor cut too deep into the multi layer circuit board If the cut trace short on a jumper header is already cut you can return the MPB to its default setting by installing a user supplied fabricated jumper Figure 2 1 MPB Parts Location Diagram top view ...

Page 13: ...cription W1 1 2 3 Jumper between pins 1 and 2 factory default selects the MPB on board crystal clock source Jumper between pins 2 and 3 selects an external clock sourceto be the MCU EXTAL input signal W2 1 2 Jumper installed or cut trace short intact factory default selects the on board VDDA power source No jumper or cut trace short enables use of an external power source connected to W2 pin 2 NOT...

Page 14: ...nternal phase locked loop or direct clock input If you install the MPB in the active probe or directly on a target system and use the target system clock as the MPB clock move the fabricated jumper to W1 pins 2 and 3 This connects the MCU EXTAL pin to the MAPI bus input pin The frequency of the external clock signal can be from 32 KHz to 16 78 MHz or to the maximum the MCU allows 1 2 3 W1 Clock So...

Page 15: ...e to W2 pin 2 Removal of the cut trace short isolates the MCU VDDA pin from the other MPB circuitry Isolation lets you connect a precision VDDA source for accurate 10 bit analog digital A D generation When connecting an external VDDA power supply to the MPB connect the power supply ground to insertion point E1 For more information on A D generation refer to the Analog To Digital Converter Referenc...

Page 16: ...on W3 pins 2 and 3 Then connect the MCU VRH pin to the external VRH source Each configuration defines the best method for connecting the MCU VRH pin to the external VRH source MPB MPFB connect via the MPFB logic analyzer connector refer to Chapter 4 for the appropriate logic analyzer pin MPB MMDS1632 connect via the VRH pin of the target MCU socket MPB Target System connect via the VRH pin of the ...

Page 17: ... to the external VRL source MPB MPFB connect via the MPFB logic analyzer connector refer to Chapter 4 for the appropriate logic analyzer pin MPB MMDS1632 connect via the VRL pin of the target MCU socket MPB Target System connect via the VRL pin of the target system MAPI bus Alternately you may remove the jumper and wire wrap directly to W4 pin 2 Connecting directly to pin 2 is an option regardless...

Page 18: ...or Figure 2 2 is a representative diagram If your target board also has A D filter capacitors you must remove either the capacitors on your board or on MPB Refer to the table below when removing MPB filter capacitors from its associated A D signal VSSA ANALOG SIGNAL MCU ADAn Figure 2 2 A D Signal Filtering Signal Capacitor AN0 C7 AN1 C5 AN2 C3 AN3 C6 AN4 C4 AN5 C2 ...

Page 19: ...r when installing the MPB on the MPFB or removing the MPB from the MPFB Sudden power surges could damage MEVB integrated circuits To install the MPB on the MPFB refer to Figure 2 3 1 Inspect all connectors for bent or damaged pins 2 Align the MPB reference mark with the MPFB reference mark 3 Rotate the MPB until the four MAPI bus connectors on its bottom mate with the MAPI bus connectors on the to...

Page 20: ...connection with serial interface After you have installed the MPB install the plastic overlay on the MPFB place the overlay over logic analyzer connectors J12 through J20 and press down Holes in the overlay slide down over plastic clips on the MPFB These clips hold the overlay in place ...

Page 21: ...be and the station module 01 RE90340W01 REV 0 and 01 RE90341W01 REV 0 are printed on the active probe cables The active probe cables come with the TCBe For more information about the active probe cables refer to the MMDS1632 Motorola Modular Development System User s Manual MMDS1632UM D Active probe box the protective enclosure for the TCB CAUTION Turn off MMDS and target system power when install...

Page 22: ... end of the 01 RE90340W01 REV 0 active probe cable to connector P5 on the MMDS control board connect the other end to connector J5 on the TCB Secure the connector clamps on TCB connectors J5 and J6 The active probe is now ready to connect to the target system refer to the PPB configuration guide for information on connecting the active probe to the target system Figure 2 4 Active Probe Interconnec...

Page 23: ... default jumper header settings for the MPB 3 2 CONFIGURING THE MPFB The MPFB includes jumper selectable options such as chip select usage memory type selection and memory size selection for the pseudo ROM sockets and reset data control NOTE The MPFB must be configured for the specific MPB Paragraph 3 2 2 provides a configuration for basic MPFB operation For a detailed description of the MPFB jump...

Page 24: ...r on pins 1 and 2 to set the pseudo ROM port size memory data width as word W5 1 2 3 Install a jumper on pins 2 and 3 to enable the PRU W6 1 2 3 W6 selects the MCU operation mode Each 3 pin jumper header set corresponds to an MCU data line While the reset pin is low the reset data values are driven on the data bus D0 D15 The MEVB reset data circuit is open drain a high state is provided via a pull...

Page 25: ...reset W17 1 2 No jumper installed the BERR signal is pulled high logic 1 via a resistor during reset W18 1 2 3 Install a jumper on pins 1 and 2 for unrestricted writes to the memory devices in the pseudo ROM sockets U2 U4 W19 1 2 3 Install a jumper on pins 1 and 2 to ground the A19 signal to the MPFB memory arrays W22 1 2 3 Install a jumper on pins 2 and 3 to select the evaluation MCU on the MPB a...

Page 26: ...4 in 635 cm lift the appropriate lever of J5 to release tension on the contacts then insert the bare wire into J5 and close the lever The MEVB requires a 5Vdc 1 0 amp power supply for operation A 1 5 amp fuse is installed on the MPFB 5Vdc power supply input line BLK RED 5V GND J5 CAUTIONS Do not use wire larger than 20 AWG in connector J5 Such wire could damage the connector Turn off MEVB power wh...

Page 27: ...nnect your BDM hardware between your computer s I O port and the BDM header on the MPFB MPFB connector J6 The drawing below shows signal assignments for connector J6 For additional information about your BDM software hardware including debugging and assembly information see the appropriate user s manual J6 DS 1 2 BERR GND 3 4 BKPT GND 5 6 FREEZE RESET 7 8 DSI 5 Vdc 9 10 DSO ...

Page 28: ...e bw Set display to black and white lpt1 Use lpt1 default lpt2 Use lpt2 lpt3 Use lpt3 or path A DOS path to directory containing the source code for source level debug Example ICD16 bw lpt2 If more than one option is given they must be separated by spaces 6 To install macros from the ICD16 debugger type at the ICD16 debug window prompt macs This command opens a window containing a list of macros w...

Page 29: ...ORBT 7830 Change wait state to zero mdf6 START Display program in PMM window pk 0 Initialize CPU registers a AA b BB e 0000 ix 0000 iy 0000 iz 0000 hr 0000 ir 0000 k 0000 sp 03fe Initialize the stack pointer sk 1 symbol TRAMBAR FFB04 symbol TRAMMCR FFB00 dmmb TRAMBAR 01 Set SRAM base address dmmb TRAMMCR 00 Enable SRAM array dmml 10000 4D6F746F Check SRAM write Motorola 68HC16 advanced MCUs dmml 1...

Page 30: ...MEVB QUICK START GUIDE 3 8 M68MPB916X1UM D ...

Page 31: ... type 4 2 LOGIC ANALYZER CONNECTOR SIGNALS The tables of this chapter describe MPFB logic analyzer connector signalsif you install an M68MPB916X1 on the MPFB The signal descriptions on J12 J20 are the logic analyzer pin outs on the plastic overlay supplied with the MPB NOTE The signal descriptions in the following tables are for quick reference only The MC68HC916X1 User s Manual MC68HC916X1UM AD c...

Page 32: ...complement negated contents of the PEPAR register 12 19 PE7 PE0 PORT E I O SIGNALS PRU replacement of the port E function 20 GND GROUND Table 4 2 Logic Analyzer Connector J8 Pin Assignments PIN MNEMONIC SIGNAL 1 2 SPARE No connection 3 OE ABG I O PRU OUTPUT ENABLE Input active high when low disables port A port B and port G outputs 4 11 PA7 PA0 PORT A I O SIGNALS PRU replacement of the port A func...

Page 33: ...PORT G I O SIGNALS PRU replacement of the port G function 20 GND GROUND Table 4 4 Logic Analyzer Connector J10 Pin Assignments PIN MNEMONIC SIGNAL 1 5V 5 VDC POWER Input voltage 5 Vdc 1 0 A used by the MEVB logic circuits To make this pin no connection remove the jumper from the header on the MPFB 2 SPARE No connection 3 AS ADDRESS STROBE Active low output signal that indicates whether a valid add...

Page 34: ...ND Table 4 6 Logic Analyzer Connector J12 Pin Assignments PIN MNEMONIC SIGNAL 1 2 SPARE No connection 3 CLKOUT SYSTEM CLOCK OUT Output signal that is the MCU internal system clock 4 BERR BUS ERROR Active low signal that indicates a memory access error has occurred 5 BKPT DSCLK BREAKPOINT Active low input signal that signals a hardware breakpoint to the CPU Development Serial Clock Clock input sign...

Page 35: ...ws asynchronous data transfers and dynamic bus sizing between the MCU and external devices 12 PULL UP Not connected pulled high through a resistor on the MPB 13 FC2 CS5 FUNCTION CODE 2 Output signal that identifies the processor state and address space of the current bus cycle CHIP SELECT 5 Output signal that selects peripheral or memory devices at programmed addresses 14 FC1 FUNCTION CODE 1 Outpu...

Page 36: ...ulate I O ports 20 GND GROUND Table 4 7 Logic Analyzer Connector J13 Pin Assignments PIN MNEMONIC SIGNAL 1 5V 5 VDC POWER Input voltage 5 Vdc 1 0 A used by the MEVB logic circuits To make this pin no connection remove the jumper from the header on the MPFB 2 SPARE No connection 3 DSACK1 DATA AND SIZE ACKNOWLEDGE 1 Active low input signal that allows asynchronous data transfers and dynamic bus sizi...

Page 37: ...CT CSM is not supported on the M68HC916X1 MCU 10 PULL UP Not connected pulled high through a resistor on the MPB 11 CLKOUT SYSTEM CLOCK OUTPUT MCU internal clock output signal 12 A23 CS10 ADDRESS BUS BIT 23 One bit of the 24 bit address bus CHIP SELECT 10 Output signal that selects peripheral or memory devices at programmed addresses 13 15 PULL UP Not connected pulled high through a resistor on th...

Page 38: ...high impedance state 6 RESET RESET Active low bi directional signal that starts a system reset 7 PULL UP Not connected pulled high through a resistor on the MPB 8 SPARE No connection 9 10 IRQ6 IRQ7 TARGET INTERRUPT REQUEST 6 7 Active low input signals from the target that asynchronously provides an interrupt priority level to the CPU IRQ1 has the lowest priority IRQ7 has the highest 11 15 GND GROU...

Page 39: ...r J17 Pin Assignments PIN MNEMONIC SIGNAL 1 4 SPARE No connection 5 8 VSSA A D GROUND A D ground reference 9 VRH VOLTAGE REFERENCE HIGH Input reference supply voltage high line must set jumper on the MPB 10 VRL VOLTAGE REFERENCE LOW Input reference supply voltage low line must set jumper on the MPB 11 AN0 ANALOG INPUT 0 Analog input line to the MCU device 12 AN1 AN5 ANALOG INPUT 1 5 Analog input l...

Page 40: ...TPUT COMPARE 1 4 Output signals that are generated when the GPT timer counter TCNT and TOC1 TOC4 comparator registers contain the same value 9 IC4 OC5 INPUT CAPTURE 4 Input signal that latches the contents of the GPT timer counter TCNT into the input capture register TI4O5 when a selected edge occurs at the pin OUTPUT COMPARE 5 Output signal that is generated when the GPT timer counter TCNT and TI...

Page 41: ...he clock signal from the SPI in slave mode the clock signal to the SPI 12 PCS0 SS PERIPHERAL CHIP SELECT 0 Active low output SPI peripheral chip select signal SLAVE SELECT Bi directional active low signal that initiates serial transmission when SPI is in slave mode causes mode fault in master mode 13 15 PCS1 PCS3 PERIPHERAL CHIP SELECT 1 3 Active low output SPI peripheral chip select signal 16 RXD...

Page 42: ...MEVB SUPPORT INFORMATION 4 12 M68MPB916X1UM D ...

Page 43: ...ter show the MAPI interface connector layout and pin assignments for MPB connectors P1 P2 P3 and P4 Figures 5 1 through 5 5 5 2 MAPI BUS CONNECTORS The connectors required to interface to the MAPI bus are 2 Robinson Nugent 2 X30 plugs P50L 060P AS TGF 2 Robinson Nugent 2 X40 plugs P50L 080P AS TGF 2 500 1 250 2 500 1 250 C L 1 1 1 1 C L C L C L C L C L Figure 5 1 MAPI Interface Connector Layout ...

Page 44: ... n 30 GND GND 31 n n 32 GND GND 33 n n 34 GND GND 35 n n 36 GND GND 37 n n 38 GND GND 39 n n 40 GND GND 41 n n 42 GND GND 43 n n 44 GND GND 45 n n 46 GND GND 47 n n 48 GND GND 49 n n 50 GND GND 51 n n 52 GND GND 53 n n 54 GND CS10 55 n n 56 GND CS9 57 n n 58 GND CS8 59 n n 60 GND CS7 61 n n 62 GND CS6 63 n n 64 GND CS5 65 n n 66 GND CS4 67 n n 68 GND CS3 69 n n 70 GND CS2 71 n n 72 GND CS1 73 n n ...

Page 45: ...D 19 n n 20 GND A1 21 n n 22 A2 A3 23 n n 24 A4 A5 25 n n 26 A6 A7 27 n n 28 A8 A9 29 n n 30 GND A10 31 n n 32 A11 A12 33 n n 34 A13 A14 35 n n 36 A15 A16 37 n n 38 A17 A18 39 n n 40 GND VPP 41 n n 42 5 Vdc GND 43 n n 44 GND GND 45 n n 46 GND GND 47 n n 48 GND GND 49 n n 50 GND GND 51 n n 52 GND GND 53 n n 54 GND GND 55 n n 56 GND GND 57 n n 58 GND GND 59 n n 60 GND Figure 5 3 MAPI Interface Conne...

Page 46: ...2 PCS3 GND 33 n n 34 PCS2 GND 35 n n 36 PCS1 GND 37 n n 38 PCS0 SS GND 39 n n 40 SCK GND 41 n n 42 MOSI GND 43 n n 44 MISO GND 45 n n 46 GND GND 47 n n 48 GND GND 49 n n 50 GND GND 51 n n 52 GND GND 53 n n 54 VSTBY GND 55 n n 56 DSO GND 57 n n 58 DSI GND 59 n n 60 HALT GND 61 n n 62 RESET GND 63 n n 64 BERR GND 65 n n 66 BKPT GND 67 n n 68 TSC GND 69 n n 70 FREEZE GND 71 n n 72 GND MAPI EXTAL 73 n...

Page 47: ... n 22 GND A0 23 n n 24 GND DSACK0 25 n n 26 GND DSACK1 27 n n 28 GND AVEC 29 n n 30 GND PMC 31 n n 32 GND DS 33 n n 34 GND AS 35 n n 36 GND SIZ0 37 n n 38 GND SIZ1 39 n n 40 GND R W 41 n n 42 GND MODCLK 43 n n 44 GND IRQ6 45 n n 46 GND IRQ7 47 n n 48 GND GND 49 n n 50 GND GND 51 n n 52 GND GND 53 n n 54 GND GND 55 n n 56 GND GND 57 n n 58 GND 5 Vdc 59 n n 60 NC Figure 5 5 MAPI Interface Connector ...

Page 48: ...MAPI SUPPORT INFORMATION 5 6 M68MPB16X1UM D ...

Page 49: ... 6 1 CHAPTER 6 SCHEMATIC DIAGRAMS 6 1 INTRODUCTION This chapter contains the M68MPB16Y1 MCU Personality Board MPB schematic diagrams These schematic diagrams are for reference only and may deviate slightly from the circuits on your MPB ...

Page 50: ...EMATIC R E 10 05 92 8 SIGNAL CROSS REFERENCES A REV DWG NO SIZE GEDABV SHEET DWG NO REV GEDTTL A D 3 1 2 C B 4 A D C 3 1 2 4 MPB916X1C 1 OF 8 A 63ASE90344W LAST_MODIFIED Fri Sep 9 11 29 14 1994 BOARD 63ASE90344W A 7 PULLUPS PULLDOWNS PERSONALITY ID 5 MODULAR ACTIVE PROBE INTERCONNECT P2 P4 3 BYPASS CAPACITORS CLEAN POWER SIGNAL FILTERS 4 MODULAR ACTIVE PROBE INTERCONNECT P1 P3 6 MCU CLOCK 2 NOTES ...

Page 51: ...LL 16 PIN ICS PIN 20 OF ALL 20 PIN ICS ETC ALL VOLTAGES ARE DC ALL CAPACITORS ARE IN UF ALL RESISTORS ARE IN OHMS 5 1 8 WATT IS AS FOLLOWS 1 UNLESS OTHERWISE SPECIFIED 2 INTERRUPTED LINES CODED WITH THE 3 DEVICE TYPE NUMBER IS FOR REFERENCE 4 SPECIAL SYMBOL USAGE 5 INTERPRET DIAGRAM IN ACCORDANCE 6 CODE FOR SHEET TO SHEET REFERENCES INPUT OUTPUT REVISION WITH THE EXCEPTION OF INSTITUTE SPECIFICATI...

Page 52: ...D 0 1UF C58 0 1UF C62 GND 0 1UF C56 0 1UF C61 5V GND GND GND GND GND VDDI VSSI 0 1UF C54 0 1UF C53 1UH L5 5V GND VDDA VSSA 0 1UF C11 W2 E1 1UH L4 L3 VDDI L1 ADC MODULE ANALOG SIGNAL FILTERS VRH VRL SELECTION ADC MODULE FOR VDDE OF MCU AND OSCILLATOR 5V AND GND DECOUPLING VDDI VSSI GENERATION BYPASS CAPACITORS CLEAN POWER SIGNAL FILTERS ADC MODULE VDDA VSSA GENERATION CUT TRACE ON BOARD 2 1 2 1 2 1...

Page 53: ... O VSTBY DSO DSI HALT RESET BERR BKPT TSC FREEZE GND GND CLKOUT GND VDD RN P50L 080S BS TGF P3 MODULAR ACTIVE PROBE INTERCONNECT P1 P3 MAPI BUS P3 MAPI BUS P1 AN 5 0 AN 5 AN 4 AN 2 AN 3 AN 1 VSTBY DSO HALT DSI BERR RESET BKPT TSC FREEZE CLKOUT MAPI EXTAL NC CS 9 CS 10 CS 7 CS 8 CS 5 CS 4 CS 6 CS 2 CS 3 CS 1 CS 0 CS 10 0 CSBOOT IC1 IC3 OC1 OC2 OC3 OC4 IC4 OC5 PWMA PWMB PAI PCLK PCS0 SS PCS1 PCS2 RX...

Page 54: ...8 D7 D5 D3 D1 VDD D11 D13 D15 D10 D12 D14 GND I O GND GND GND GND RN P50L 060S BS TGF VPP4 P4 VSSA MAPI BUS P4 MAPI BUS P2 MODULAR ACTIVE PROBE INTERCONNECT P2 P4 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 ...

Page 55: ...1C 6 OF 8 A 63ASE90344W LAST_MODIFIED Fri Sep 9 11 38 12 1994 BOARD 63ASE90344W A NOTE 1 PLACE THE CAP BETWEEN VDDSYN XFC AS CLOSE TO MCU PINS AS POSSIBLE 2 THE CAP BETWEEN XFC VSSI IS OPTIONAL MCU CLOCK 14 PIN DIP SOCKET FOR 8 OR 14 PIN CANS DIPS 11 8 2 1 2 1 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 8...

Page 56: ...2 3 4 5 7 8 9 15 14 13 12 11 10 16 6 8 7 6 5 4 3 2 1 15 14 13 12 11 10 16 9 A 2 A 1 NC NC NC NC NC NC NC CS 10 0 AVEC HALT MODCLK DSACK0 RMC CS 7 CS 8 CS 9 NC NC NC NC CSBOOT A 9 220K A 8 A 10 NC NC NC NC NC A 7 A 6 A 5 A 4 A 3 NC A 18 0 220K IRQ 6 IRQ 7 SCK PCS0 SS PCS1 PCS2 MOSI MISO IRQ 7 6 NC 1M 1M PCS3 RXD TXD PAI PWMB PWMA PCLK IC1 IC2 IC3 IC4 OC5 OC4 OC3 OC2 OC1 6D1 5C4 4B1 5B4 6D4 5C4 5C4 ...

Page 57: ...6D4 DSACK0 5C4 7C4 DSACK1 5C4 6D4 OC2 4C1 6B1 7B4 OC1 4C1 6B1 7B4 MOSI 4B1 6C4 7B4 MODCLK 5B4 6D4 7C4 MISO 4B1 6C4 7A4 MAPI VRL 3B4 5C1 MAPI VRH 3B4 5C1 MAPI EXTAL 4A1 6A1 IRQ 7 6 5B4 6D4 7A4 IC4 OC5 4C1 6B1 7B4 IC3 4C1 6B1 7C4 IC2 4D1 6C1 7C4 IC1 4D1 6C1 7C4 HALT 4B1 7C4 FREEZE 4A1 6D1 DSO 4B1 6D1 DSI 4B1 6D1 OC3 4C1 6B1 7B4 OC4 4C1 6B1 7B4 PAI 4C1 6B1 7B1 PCLK 4C1 6B1 7B1 PCS0 SS 4C1 6B4 7B4 VRH...

Page 58: ...SCHEMATIC DIAGRAMS 6 10 M68MPB916X1UM D ...

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