TB-FMCL-MIPI Hardware User Manual
18
Rev.3.01
shown:
1
3.3V
2
3
4
5
6
7
8
1
2.5V
2
3
4
5
6
7
8
1
VADJ
2
3
4
5
6
7
8
1
VUSER
2
3
4
5
6
7
8
Figure 9-2 MIPI GPIO Voltage Select Options
Each GPIO group has a header for voltage selection; MIPI PORT A (CSI-2) MIPI_AUXIO_(1-4) uses
header J12, and MIPI PORT B (DSI) MIPI_AUXIO_(5-8) uses header J19.
The direction of each of the eight GPIOs
is determined by the Carrier Card FPGA via the MIPI FMC’s I2C
I/O Expander (Texas Instruments, PCA9534A). The I/O Expander is powered by 3V3_AUX and is
located on the dedicated FMC I2C bus at address: 01111xx (xx is determined by the FMC slot signals
GA[0:1]; GA0
→ A1, GA1 → A0). The I/O Expander’s GPIOs default to input upon power up. Once
configured, when
direction control pin is “high”, the GPIOs are outputs driven to the MIPI Port connector.
When the direction control pin is “low”, the GPIOs are inputs driven from the MIPI Port connector.
To help avoid contention, the recommended configuration sequence for the I/O Expander and Buffers
are as follows:
Table 9-1 GPIO Signals: Recommended sequencing
Stage
Action
Signals
T0
Power-Up, FPGA Configuration
MIPI_AUXIO_nOE1-4 = 1
MIPI_AUXIO_nOE5-8 = 1
DIR_MIPI_AUXIO_LPC[1:8]= X (d
on’t Care)
MIPI_AUXIO_LPC
[1:8] = X (don’t care)
Notes:
1. Both OE signals have resistor pull-ups to VADJ
2. Direction control signals have resistor pull-downs
T1
Program I/O Expander
MIPI_AUXIO_nOE1-4 = 1
MIPI_AUXIO_nOE5-8 = 1
DIR_MIPI_AUXIO_LPC[1:8]= As required
T2
Start GPIO Signals
MIPI_AUXIO_nOE1-4 = 1
MIPI_AUXIO_nOE5-8 = 1
DIR_MIPI_AUXIO_LPC[1:8]= As required
MIPI_AUXIO_LPC[1:8] = As required
T3
Enable Level Translators
MIPI_AUXIO_nOE1-4 = 0
MIPI_AUXIO_nOE5-8 = 0
DIR_MIPI_AUXIO_LPC[1:8]= As required
MIPI_AUXIO_LPC[1:8] = As required
