TB-FMCL-MIPI Hardware User Manual
19
Rev.3.01
9.3. MIPI I2C Bus
Each MIPI Port connector provides a standard I2C bus to any peripheral device that may be able to use
it (typically devices that do not utilize the MIPI BTA capability). Each connector receives its own set of
SelectIO pin assignments on the FMC connector, thus there is no I2C bus sharing on either MIPI port,
providing complete flexibility for MIPI device slave address assignment. The I2C bus of each port is IO
Voltage level selectable through headers J6 for the CSI port (MIPI Port A) and header J17 for the DSI
port (MIPI Port B). The jumper selection positions are identical to that of the GPIO selector headers
J12 and J19, detailed earlier in Figure 9-2. Note that the I2C translation buffer only supports voltages
down to 1.65V; the user must not to select a lower VUSER or VADJ voltage if the MIPI I2C is used.
However, if the I2C is not used, it is not harmful for VUSER or VADJ, if selected, to be below 1.65V as
long as the I2C port is not expected to operate.
10.
Connectors
There are three main connectors on the TB-FMCL-MIPI card. One LPC FMC connector (J1) provides the
FMC host carrier interconnection, and the other two connectors (J5 and J16) are two right-angle MIPI
port sockets facing off the front edge (I/O window) of the FMC module. Additionally, for debug and
development access, two right angle headers, J15, and J18, located behind the MIPI port sockets and
facing out to the board side edges, provide access to the MIPI GPIO and I2C signals as well as VUSER
and 12V0.
10.1. LPC FMC Connector to Host Carrier Board
The LPC FMC connector (J1) used to mate to the Host Carrier Board is a Samtec ASP-134604-01. Only
the 160-pin LPC positions are populated, however, the module may be installed on a supported HPC
receptacle.
Table 10-1 shows the FMC connector pin assignment. In this table the C2M direction means
Carrier-to-Mezzanine, representing an input to the FMC. The M2C direction means Mezzanine-to-Carrier,
representing an output from the FMC. BIDIR identifies those signals whose direction can be application
selected. Signal Direction and Description in brackets represent MIPI port option assembly. Default
assembly shown is CSI-DSI (MIPI 1
– MIPI 2). Unused LAxx, DPx, and GBTCLKx signals are not
included in the table and are left unconnected. Power and GND pins are also not included; refer to
Figure 3-1 for power and ground pin connections.
FPGA IO allocations to FMC IO pins are platform specific and not included in the following table.
Please refer to the user manual of the particular FMC carrier host FPGA platform being used for the
mapping of FMC IOs to FPGA banks and pins.
