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TB-FMCL-MIPI Hardware User Manual

Rev.3.01

9. MIPI IO Signals

9.1. MIPI D-PHY Lanes

Each MIPI connector, whether input (CSI-2) or output (DSI), provides five differential pairs that are

designed to interface to 100-ohm differential wiring to the MIPI peripheral. The differential pairs are

assigned per Samtec

’s recommendations for the LSHM series where each pair occupies adjacent pins

bounded on both sides by GND pins. For signal integrity reasons, in the 20-pin by 2-row connector pin

matrix, the high-speed differential lanes occupy the inside row

, or “short” path (ROW 1), of the connector.

All five lanes from a connector to PHY device IO pads are delay matched to 10ps to minimize the PCB

impact on signal/clock timing relationship. Both the CSI and DSI port traces are approximately 31mm in

length, measured from the Meticom PHY pins to the LSHM connector.

9.2. MIPI GPIO Signals

Each MIPI connector is supplied with four GPIO signals that are supplied from SelectIO pins on the FMC

connector, as per the following diagram:

GA1

3.3V AUX

MIPI PORTA

MIPI PORTB

GA0

3.3V AUX

ADDR: 01111xx

SDA

SCL

BI-DIR
LEVEL

SHIFTER

VADJ

A1
A2

B1
B2

OEn

BI-DIR
LEVEL

SHIFTER

VADJ

A1
A2

B1
B2

OEn

DIR_MIPI_AUXIO_LPC3

DIR_MIPI_AUXIO_LPC4

MIPI_AUXIO_LPC1

MIPI_AUXIO_LPC2

MIPI_AUXIO_nOE1-4

MIPI_AUXIO_LPC3

MIPI_AUXIO_LPC4

MIPI_AUXIO1

MIPI_AUXIO2

MIPI_AUXIO3

MIPI_AUXIO4

I2C I/O

EXPANDER

DIR_MIPI_AUXIO_LPC3

DIR_MIPI_AUXIO_LPC4

DIR_MIPI_AUXIO_LPC5

DIR_MIPI_AUXIO_LPC6

DIR_MIPI_AUXIO_LPC7

DIR_MIPI_AUXIO_LPC8

DIR_MIPI_AUXIO_LPC1

DIR_MIPI_AUXIO_LPC2

BI-DIR
LEVEL

SHIFTER

VADJ

A1
A2

B1
B2

OEn

BI-DIR
LEVEL

SHIFTER

VADJ

A1
A2

B1
B2

OEn

DIR_MIPI_AUXIO_LPC7

DIR_MIPI_AUXIO_LPC8

MIPI_AUXIO_LPC5

MIPI_AUXIO_LPC6

MIPI_AUXIO_nOE5-8

MIPI_AUXIO_LPC7

MIPI_AUXIO_LPC8

MIPI_AUXIO5

MIPI_AUXIO6

MIPI_AUXIO7

MIPI_AUXIO8

DIR_MIPI_AUXIO_LPC5

DIR_MIPI_AUXIO_LPC6

VUSER

3V3

2V5

VADJ

VUSER

3V3

2V5

VADJ

Figure 9-1 GPIO SIGNALS TO EACH MIPI PORT

The VADJ IO voltage domain of the FMC is level shifted to the user selected MIPI IO voltage domain

using Texas Instruments SN74AVC2T245 bi-directional dual-voltage transceivers. These devices can

operate to voltages as low as 1.2V, allowing the MIPI GPIO signals to support VADJ or VUSER down to

1.5V (actual minimum VADJ is 1.65V due to I2C translator limitations). Two FPGA pins on the FMC

connector control the output enable (OEn) of the level shifters (OEn=1 results in Hi-Z on each side of

translator). Each MIPI connector GPIO group can have its MIPI IO voltage selected from four options as

Summary of Contents for TB-FMCL-MIPI

Page 1: ...TB FMCL MIPI Hardware User Manual 1 Rev 3 01 TB FMCL MIPI Hardware User Manual Rev 3 01 ...

Page 2: ...0 5 25 2015 Reviewed and updated General Release RH Rev 1 99 8 26 2015 Reviewed Updated for PA 10087 0x Rev2 0 Submitted for review ST Rev 2 00 9 14 2015 Updated Released ST Rev 3 00 11 30 2015 Updated with new connector information ST Rev 3 01 6 30 2016 Updated 2 Overview 8 2 HS Mode Interface Updated Figure 4 1 Figure 7 1 Figure 10 1 Amano ...

Page 3: ... Device to FMC Interface 15 8 1 PHY Device Overview 15 8 2 HS Mode Interface 15 8 3 LP Mode Interface 16 8 4 PHY Control 16 9 MIPI IO Signals 17 9 1 MIPI D PHY Lanes 17 9 2 MIPI GPIO Signals 17 9 3 MIPI I2C Bus 19 10 Connectors 19 10 1 LPC FMC Connector to Host Carrier Board 19 10 2 MIPI Front Edge I O Window Receptacles 24 10 3 MIPI GPIO and I2C Debug Headers 26 11 FMC Facility I2C Bus 27 11 1 FM...

Page 4: ...lect Options 18 Figure 10 1 Resistor for connection to TB 7V 2000T LSI 23 Figure 10 2 MIPI Connectors Faceplate View 24 Figure 10 3 Axial removal vs zippering picture courtesy of Samtec 24 Figure 10 4 MIPI Debug header side access views 26 Figure 15 1 Default Jumper Positions and Header Orientation 31 List of Tables Table 1 1 Accessories 8 Table 8 1 MIPI PHY Mode Settings 16 Table 9 1 GPIO Signals...

Page 5: ...fety instructions that must be observed After reading through this manual be sure to always keep it handy The following conventions are used to indicate the possibility of injury damage and classify precautions if the product is handled incorrectly Indicates the high possibility of serious injury or death if the product is handled incorrectly Indicates the possibility of serious injury or death if...

Page 6: ...peed do not put your hand close to it Otherwise it may cause injury to persons Never touch a rotating cooling fan Do not place the product on unstable locations Otherwise it may drop or fall resulting in injury to persons or failure If the product is dropped or damaged do not use it as is Otherwise a fire or electric shock may occur Do not touch the product with a metallic object Otherwise a fire ...

Page 7: ...bility acts by a third party or other accidents the customer s willful or accidental misuse or use under other abnormal conditions 2 Secondary impact arising from use of this product or its unusable state business interruption or others 3 Use of this product against the instructions given in this manual 4 Malfunctions due to connection to other devices Tokyo Electron Device Limited assumes no resp...

Page 8: ...I O Window Each side utilizes a PHY device designed to be compatible with the MIPI D PHY Specification 1 00 00 September 2009 meeting the nominal data throughput of 1 Gbit s per lane The TB FMCL MIPI does not utilize any of the high speed serial DPx data links and GBTCLKs provided in the FMC standard so present data speed is limited to the capabilities of HR and HP SelectIO of Xilinx FPGAs The TB ...

Page 9: ...hrough 3 3V using voltage level translators 12V power up to 200mA per MIPI PTC self resetting fuse protected Cooper PTS120615V050 LDO regulators for PHYs Texas Instruments TPS74701 generating local 2 5V and 1 2V FMC Configuration EEPROM Micron M24C02 2Kb I2C EEPROM with GA0 1 address selection Voltage presence LED indicators One green LED for each on board voltage rail An excerpt from ANSI VITA 57...

Page 10: ...Max Draw 60mA LP D_P LP C_P LP B_N LP B_P LP C_N LP D_N HS E_P N HS D_P N HS C_P N HS B_P N HS A_P N D PHY A_P N D PHY B_P N D PHY C_P N D PHY D_P N D PHY E_P N D PHY A_P N D PHY B_P N D PHY C_P N D PHY D_P N D PHY E_P N 1 2V 2 5V 1 2V 2 5V 12 0V 3 3V VADJ 2 5V 1 2V STATUS LEDs I2C SDA I2C SCL All CSI 2 and DSI MIPI Port SLVS control and I2C signals have ESD protection devices not shown Four optio...

Page 11: ...E SELECTOR J19 MIPI PORTB DSI CONNECTOR J16 MIPI PORTA CSI CONNECTOR J5 MIPI PORTA GPIO DEBUG HDR J15 FMC LPC CONNECTOR J1 MIPI PORTA PORTB PIN SWAP HDR J3 MIPI PORTA MIPI AUX IO VOLTAGE SELECTOR J12 MIPI PORTB I2C VOLTAGE SELECTOR J17 VUSER VOLTAGE SELECTOR J9 MIPI PORTA I2C VOLTAGE SELECTOR J6 Figure 5 1 Photo of TB FMCL MIPI Side 1 ...

Page 12: ...TB FMCL MIPI Hardware User Manual 12 Rev 3 01 Figure 5 2 Photo of TB FMCL MIPI Side 2 ...

Page 13: ...ng connector for C L 63 00 66 00 10 90 65 60 54 60 2 20 43 04 61 30 18 54 3 00 57 90 59 05 58 30 Ø2 7 6plcs 3 00 0 80 C L Figure 6 1 TB FMCL MIPI Board Dimensions mm Notes Board outline features conform to VITA57 1 air cooled commercial grade single width modules MIPI connectors are pitched at 24 50mm center to center CSI position is defined as MIPI Port A DSI position is defined as MIPI Port B Bo...

Page 14: ...ir FMC LPC CONNECTOR 12V 0 5A PTC 3 3V 0 5A PTC 3 3V AUX EEPROM I2C I O EXPANDER VADJ Adjustable Buck Switching Regulator GPIO LEVEL SHIFTERS I2C LEVEL SHIFTERS GPIO LEVEL SHIFTERS VADJ I2C LEVEL SHIFTERS VUSER 3V3 2V5 VADJ 3V3 2V5 VADJ VUSER VUSER LDO Regulator 2V5 LDO Regulator 1V2 1V5 1V8 2V5 3V3 VUSER SELECTION MIPI PORT 1 IO VOLTAGE SELECTION MIPI PORT A MIPI PORT B 12V0 3V3_AUX MIPI PORT 2 I...

Page 15: ... series of six green LEDs are located in a row on Side 2 solder side so they are visible when the card is installed on an FMC carrier The LEDs indicate the presence of the various supply rails and under normal conditions all six LEDs should be lit when the card is powered up The following diagram of the solder side displays the row of LEDs and their meaning 12V0 3V3 3V3_VAUX 2V5 1V2 VADJ VUSER Fig...

Page 16: ...roup of four control inputs to the host which govern the operation of the MIPI link Two pins called GPIO 1 and GPIO 2 set the operating state of the PHY Another input pin BTA enables the Bus Turn Around in LP mode and is used for host access to status and control registers within the peripheral device The final input pin called PINSWAP is a three mode input which controls the differential polarity...

Page 17: ...HIFTER VADJ DIR1 DIR2 A1 A2 B1 B2 OEn DIR_MIPI_AUXIO_LPC3 DIR_MIPI_AUXIO_LPC4 MIPI_AUXIO_LPC1 MIPI_AUXIO_LPC2 MIPI_AUXIO_nOE1 4 MIPI_AUXIO_LPC3 MIPI_AUXIO_LPC4 MIPI_AUXIO1 MIPI_AUXIO2 MIPI_AUXIO3 MIPI_AUXIO4 I2C I O EXPANDER DIR_MIPI_AUXIO_LPC3 DIR_MIPI_AUXIO_LPC4 DIR_MIPI_AUXIO_LPC5 DIR_MIPI_AUXIO_LPC6 DIR_MIPI_AUXIO_LPC7 DIR_MIPI_AUXIO_LPC8 DIR_MIPI_AUXIO_LPC1 DIR_MIPI_AUXIO_LPC2 BI DIR LEVEL SH...

Page 18: ... high the GPIOs are outputs driven to the MIPI Port connector When the direction control pin is low the GPIOs are inputs driven from the MIPI Port connector To help avoid contention the recommended configuration sequence for the I O Expander and Buffers are as follows Table 9 1 GPIO Signals Recommended sequencing Stage Action Signals T0 Power Up FPGA Configuration MIPI_AUXIO_nOE1 4 1 MIPI_AUXIO_nO...

Page 19: ...t angle MIPI port sockets facing off the front edge I O window of the FMC module Additionally for debug and development access two right angle headers J15 and J18 located behind the MIPI port sockets and facing out to the board side edges provide access to the MIPI GPIO and I2C signals as well as VUSER and 12V0 10 1 LPC FMC Connector to Host Carrier Board The LPC FMC connector J1 used to mate to t...

Page 20: ...N LA20_N H25 C2M_LVDS_HS3_P LA21_P C2M LVDS MIPI DSI PHY HS Channel B H26 C2M_LVDS_HS3_N LA21_N D20 C2M_LVDS_HS4_P LA17_CC_P C2M LVDS MIPI DSI PHY HS Channel A D21 C2M_LVDS_HS4_N LA17_CC_N H4 CLK0_M2C_P CLK0_M2C_P M2C LVDS Optional MIPI CSI PHY HS Channel A H5 CLK0_M2C_N CLK0_M2C_N G2 CLK1_M2C_P CLK1_M2C_P C2M LVDS Optional MIPI DSI PHY HS Channel A G3 CLK1_M2C_N CLK1_M2C_N inrevium strap option r...

Page 21: ... 1 PHY BTA Enable C11 CSI_PNSWP_LPC LA06_N C2M LVCMOS VADJ MIPI 1 PHY Pin Swap Enable G33 DSI_GPIO0_LPC LA31_P C2M LVCMOS VADJ MIPI 2 PHY GPIO Mode control bits G34 DSI_GPIO1_LPC LA31_N C2M LVCMOS VADJ C26 DSI_BTA_LPC LA27_P C2M LVCMOS VADJ MIPI 2 PHY BTA Enable C27 DSI_PNSWP_LPC LA27_N C2M LVCMOS VADJ MIPI 2 PHY Pin Swap Enable MIPI GPIO and I2C Signals D14 MIPI_AUXIO_LPC1 LA09_P per MIPI_AUX_DI ...

Page 22: ...LPC_OD LA15_N C2M LVCMOS OD VADJ MIPI Port B I2C Clock H19 I2C_SDA_DSI_LPC_OD LA15_P BIDIR LVCMOS OD VADJ MIPI Port B I2C Data FMC Facility Signals C30 CLK_FMC_SCL_OD SCL C2M LVTTL OD FMC IPMI EEPROM Clk C31 FMC_SDA_OD SDA BIDIR LVTTL OD FMC IPMI EEPROM Data C34 GA0 GA0 C2M LVTTL FMC IPMI EEPROM slave address select MSB D35 GA1 GA1 C2M LVTTL FMC IPMI EEPROM slave address select LSB D1 FMC_PG_C2M P...

Page 23: ...ev 3 01 Note If this FMC is to be connected to the inrevium TB 7V 2000T LSI then populate R180 and R181 and depopulate R178 and R179 populate R184 and R185 and depopulate R182 and R183 Figure 10 1 Resistor for connection to TB 7V 2000T LSI ...

Page 24: ...odules a MIPI camera sensor and or low power MIPI mobile display panel can be directly supported without need for additional external connections The two receptacles are located side by side at the faceplate edge with pinout as shown in the front view below in typical components down orientation 39 40 1 2 PORT A DFT CSI DFT DSI PORT B 39 40 1 2 Figure 10 2 MIPI Connectors Faceplate View Note These...

Page 25: ...TP2 6 MIPI_SLVS_IN4_P 7 GND 8 GND 9 LOOP_N 10 MIPI_SLVS_IN3_N 11 LOOP_P 12 MIPI_SLVS_IN3_P 13 GND 14 GND 15 MIPI_AUXIO_4 16 MIPI_SLVS_IN2_N 17 MIPI_AUXIO_3 18 MIPI_SLVS_IN2_P 19 GND 20 GND 21 MIPI_AUXIO_2 22 MIPI_SLVS_IN1_N 23 MIPI_AUXIO_1 24 MIPI_SLVS_IN1_P 25 GND 26 GND 27 I2C_SDA_MIPI_CSI_OD 28 MIPI_SLVS_IN0_BTA_N 29 CLK_I2C_SCL_MIPI_CSI_OD 30 MIPI_SLVS_IN0_BTA_P 31 GND 32 GND 33 VUSER 34 VUSER...

Page 26: ...OP_P and LOOP_N provide a passive method for two adapters to connect Reserved for future use 10 3 MIPI GPIO and I2C Debug Headers The MIPI debug headers are right angle 2mm 2x5 box headers that provide access to the GPIO and I2C signals presented on the LSHM MIPI sockets For signal integrity reasons none of the MIPI lanes are accessible on these headers J15 provides access to the CSI port and J18 ...

Page 27: ...permanently enabled for writing The FMC identification EEPROM is programmed at the factory to enable automated identification verification and configuration of Main Board parameters typically VADJ voltage level The contents of the EEPROM are described in Appendix A Note The user must be cognizant that the FMC I2C EEPROM is always write enabled As it contains critical information required for corre...

Page 28: ...I CSI xx 03 for DSI DSI FRU File ID 1 0 Hardware Revision 6 Variable MAC Address 6 00 00 00 00 00 00 Multi Record Information VITA Subtype 0 Record Field Size Data Description Vendor OUI 3 0x0012A2 Fixed value of 0x0012A2 Subtype Version 1 0x00 7 4 type main definition type 3 0 version current version Size Connectors Clock Dir 1 0x0C 7 6 size single width 5 4 P1 size LPC 3 2 P2 size not fitted 0 c...

Page 29: ...of 1mV 10Hz to 30MHz 50mV Minimum Current Draw 2 0x001E In units of 1mA 30mA Maximum Current Draw 2 0x0096 In units of 1mA 150mA DC Load Record 12P0V Field Size Data Description Output Information 1 0x02 Bit map containing output number etc 12V Nominal Voltage 2 0x04B0 In units of 10mV 12V Minimum Voltage 2 0x0474 In units of 10mV 11 4V Maximum Voltage 2 0x04EC In units of 10mV 12 6V Ripple and No...

Page 30: ...In units of 1mV 10Hz to 30MHz Minimum Current Load 2 0x0000 In units of 1mA Maximum Current Load 2 0x0000 In units of 1mA DC Output Record VREF_B_M2C DOES NOT EXIST LPC Field Size Data Description Output Information 1 0x05 Bit map containing output number etc Nominal Voltage 2 0x0000 In units of 10mV Minimum Voltage 2 0x0000 In units of 10mV Maximum Voltage 2 0x0000 In units of 10mV Ripple and Noi...

Page 31: ...der Function Selected J3 1 2 DSI_MIPI_PINSWP controlled by FPGA 3 4 CSI_MIPI_PINSWP controlled by FPGA J6 7 8 MIPI PORT A CSI I2C set to VUSER IO voltage J9 5 6 VUSER set to 1 8V J12 7 8 MIPI PORT A MIPI_AUXIO_ 1 4 set to VUSER IO voltage J17 7 8 MIPI PORT B DSI I2C set to VUSER IO voltage J19 7 8 MIPI PORT B MIPI_AUXIO_ 5 8 set to VUSER IO voltage J3 2 3 4 5 6 7 8 1 J12 2 3 4 5 6 7 8 1 J17 2 3 4 ...

Page 32: ...01 Inrevium Company URL http www inrevium com http solutions inrevium com E mail psd support teldevice co jp HEAD Quarter Yokohama East Square 1 4 Kinko cho Kanagawa ku Yokohama City Kanagawa Japan 221 0056 TEL 81 45 443 4031 FAX 81 45 443 4063 ...

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