Application Note
page 8 of 33
V1.7
2022-08-01
XENSIV™ BGT60LTR11AIP shield
60 GHz radar system platform
Hardware description
The integrated target detector circuits in the MMIC indicate the detection of movement in front of the radar and
the direction of movement with two digital signals (BGT_TARGET_DET and BGT_PHASE_DET). See section 3.8 for
more details. The detector circuit offers a user-configurable hold-time for maximum flexibility.
Figure 5
BGT60LTR11AIP MMIC block diagram
Figure 6
Package and pin-signal assignment of the BGT60LTR11AIP MMIC
VDD_RF
A2
QS3
B1
PDET
D1
QS4
M1
SPIDO
B6
VTUNE
C1
IFQ
K1
TDET
E1
PLL_TRIG
G1
VDD_PLL
M2
QS1
M6
VDD_RF
B2
SPIDI
B5
GND
M4
GND
N4
GND
N6
GND
N1
GND
B3
GND
A3
IFQAI
M5
GND
B4
GND
N3
XOSC_AI
J1
SPIRST_N
A5
GND
A6
DIV_O
F1
GND
A1
IFI
L1
XOSC_AO
H1
VDD_PLL
N2
GND
A4
QS2
N5
GND
M3
SPICLK
C6
SPICS
D6
IFIAO
E6
IFIAOX
F6
IFIAIX
G6
IFIAI
H6
IFQAO
J6
IFQAOX
K6
IFQAIX
L6
U1
BGT60LTR11AiP
Xosc_ao
Xosc_ai
QS1
QS2
QS3
QS4
BGT_SCK_1.5_A
BGT_SELECT_1.5_A
BGT_MISO_1.5_A
BGT_MOSI_1.5_A
BGT_RTSN_1.5_A
BGT_PLL_TRIG_1.5
BGT_VTUNE
VTUNE
BGT_TARGET_DET
BGT_DIV
BGT_PHASE_DET
GND
VDD_RF
VDD_PLL
IF1i_P
IF1i_N
IF1q_P
IFI
IFQ
IFQx_PostLPF
IFQ_PostLPF
IFIx_PostLPF
IFI_PostLPF
IF1q_N
