Application Note
page 10 of 33
V1.7
2022-08-01
XENSIV™ BGT60LTR11AIP shield
60 GHz radar system platform
Hardware description
Figure 9
The crystal circuit on the BGT60LTR11AIP shield
3.5
External capacitors
The BGT60LTR11AIP MMIC is duty-cycled and performs a sample and hold (S&H) operation for lower power
consumption. The S&H switches are integrated in chip at each differential IQ mixer output ports. They are
controlled synchronously via the internal state machine. The capacitors between S&H and the high-pass filter
(HPF) are external (Figure 10). C10, C11, C14 and C15 are 5.6 nF capacitors used as
“h
old
”
capacitors for the S&H
circuitry. They can be configured for different pulse width settings, as shown in Table 2. C8, C9, C12 and C13 are
the DC blocking (or High Pass) capacitors. They should have a value of 10 nF in order to get a high-pass of 4 Hz
(if internal high pass resistor, R
HP
= 4 M
Ω
). It is not recommended to use higher values as it will affect the Analog
Base Band (ABB) settling time. The DC blocking capacitors are important because the mixer output has a
different DC voltage than the internal ABB. In Figure 10 the external hold
(
𝐶
ℎ𝑜𝑙𝑑
)
and high-pass capacitors
(
𝐶
𝐻𝑃
)
are shown for all four branches in the differential IQ configuration.
Figure 10
External capacitors
Table 2
Recommended hold capacitors (C10, C11, C14 and C15) for different pulse widths
Pulse width (µs)
Hold capacitor value (nF)
3
4.7
4
5.6
5 (default)
5.6 (default)
10
15
Charging time of the hold capacitor
(
𝐶
ℎ𝑜𝑙𝑑
)
is limited to the selected pulse width. Shorter pulse widths require
smaller
𝐶
ℎ𝑜𝑙𝑑
to get it ~ 90% charged during one pulse. Rise-time is controlled by the
𝐶
ℎ𝑜𝑙𝑑
itself and the
internal mixer output resistance
(𝑅
𝑚𝑖𝑥𝑒𝑟_𝑜𝑢𝑡
)
of 300
Ω
in each branch.
1
3
2
4
Y1
FH3840024Z
GND
GND
GND
C16
11pF
C17
16pF
GND
Xosc_ai
Xosc_ao
IF1i_P
IF1q_P
IFI_PostLPF
IFQ_PostLPF
C8
10nF
C9
10nF
GND
GND
C10
5.6nF
C11
5.6nF
IF1q_N
IF1i_N
IFIx_PostLPF
IFQx_PostLPF
C12
10nF
C13
10nF
GND
GND
C14
5.6nF
C15
5.6nF
