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Infineon IRPS5401, User Manual

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Infineon IRPS5401 User Manual Download Page 25

  

 

Application Note 

25 of 63 

V 1.2  

 

 

2018-12-12

 

 

5 Output PMIC Controller/ IRPS5401 

User guide with DB295 and DB296 demo boards 

   

 

Figure 32

 

VSENSE on layers 1, 3 

5.4

 

VIN Decoupling 

This screen grab shows that MLCC caps are placed directly aside the TDA21240 to create the shortest loop 
possible for the current path for the FETs in the power stage. 
 

 

Figure 33

 

MLCC capacitors aside TDA21240 

Summary of Contents for IRPS5401

Page 1: ...e device only and shall not be regarded as a description or warranty of a certain functionality condition or quality of the device This application note is intended to provide a description of the ope...

Page 2: ...8 Under Voltage Settings 18 4 9 Over Temperature 19 4 10 Scaling of VOUT 20 5 External Power Stage 22 5 1 ISENSE AMP Gain Settings 23 5 2 Layout Concerns 24 5 3 VSENSE FEEDBACK 24 5 4 VIN Decoupling...

Page 3: ...T IRPS5401 demo boards IRPS5401 is a 56 pin 7x7 mm PMIC It has 4 switching outputs and 1 LDO output SW A and SW B have a max rated current of 2 A SW A can be configured to drive an external power stag...

Page 4: ...dongle 1 you should be able to hit the Auto populate button 2 and have the GUI recognize and populate the IRPS5401 information 3 You can also use the address scan feature 4 to scan all addresses and s...

Page 5: ...Lock register Figure 4 PMBus address Figure 5 I2C address After the addresses have been updated in REG 0x0020 you will need to right click on the device 1 to bring up the address editor dialog box 2 t...

Page 6: ...1 ADDR_PROT Pin The base I2C and PMBus address that is placed in NVM can be offset by up to fifteen 15 so that up to sixteen 16 IRPS5401 devices with a common NVM address can be placed on a common I2...

Page 7: ...t the offset Figure 8 Setting the resistor This table shows the offset given for a specific resistor value The I2C and PMBus address will be offset by the same value NOTE the address can t be offset a...

Page 8: ...3 11 00 k 14 12 10 k 15 2 2 TEST ADDRESS 0Ah If the MTP pin pin 54 is connected to VCC or any voltage greater than 3 3 V during POR NVM will not load into the working registers and the I2C address wil...

Page 9: ...IT is read only and is set to 0 72 A The OV_WARN and FAULT UV_WARN and FAULT are all read only and are a percentage of the VOUT value set in REG 0x1420 7 0 ldo_target_vout The lsb is 15 625 mV So a va...

Page 10: ...s are READ ONLY for the LDO A read command will report back the percentage of VOUT shown in the table below POWER_GOOD_ON and OFF is a read only command in tracking mode Table 2 Address offset table M...

Page 11: ...most important considerations for the layout is the path length and loop area for the current path from the input capacitors to the FET switches C85 in the figure to the left is a 1 F 0402 multi laye...

Page 12: ...mmands sent to SW A B and D will read back the value sent in the ignored command SW A FREQUENCY The user can set the FSW of SW A to be of SW C by sending a FREQUENCY_SWITCH command to SW A that is les...

Page 13: ...tage that will cause the AOT pulse to start This is usually set to 1 3 mV Figure 15 Diode_emu_threshold diode_emu_pw is the time that the HS FET is on after AOT is activated It is usually set to 1 The...

Page 14: ...urate Do not send READ_IOUT commands while in AOT Mode 4 3 External Sync The IRPS5401 has a sync input pin 52 that can be used to set the FSW to an external clock The threshold levels are LVTTL 0 8V m...

Page 15: ...is based on the output of a comparator that is looking directly at the Rdson To ensure OC_FAULT_LIMIT accuracy the comparator is trimmed during ATE Test to tolerances of 10 at 3 A for the 2 A outputs...

Page 16: ...UT sense The gain error is 5 The chart below shows the contribution for each source offset and gain from 5 load to 100 load for the 4 A outputs Figure 22 Current reporting 4 6 Over Voltage Settings at...

Page 17: ...400 mV above VOUT in 50 mV increments The user sets the relative threshold by sending a VOUT_OV_FAULT_LIMIT value that is greater than the VOUT_COMMAND by the required threshold If the VOUT_COMMAND i...

Page 18: ...V or any value less than 0 25 V the relative o V threshold will be used as VOUT transitions down to 0 V Then the fixed_ovp_thresh is used while waiting for a new VOUT_COMMAND 4 8 Under Voltage Settin...

Page 19: ...ad Only RO register xx56h 6 4 0 50 mV 1 100 mV up to 7 400 mV If 1 2 scaling is used the relative UVP threshold is 2x the value shown The UV_WARN_LIMIT is not a relative threshold It is the absolute v...

Page 20: ...with an internal 20 k resistor So anytime FB_x is not sitting at 1V a bias current will be sourced or sunk by the FB_x pin The worst case error will be with VOUT 5 V Internally the DAC will be set to...

Page 21: ...PS5401 User guide with DB295 and DB296 demo boards to 5 V the additional 75 A added to the 2 5 mA that is already in the resistor will cause the voltage drop on R42 to be 2 513 V VOUT will be 5 013 V...

Page 22: ...I will update Switcher A to Switcher A Ext Figure 28 Design tool view In EXT mode BOOT_A and PHASE_A are no connects PWM_A is used to drive the PWM input of an external power stage The ISEN_A and ISEN...

Page 23: ...ds to make sure the MAX current required to be sensed does not exceed this limit 0 7 V 10 mV A 70 A Since the DB295 is rated for 50 A max the ecs_gain is limited to 10x 1 mV A 10 50 A 500 mV at the OC...

Page 24: ...rent sense connections for inductior current sensing on layers 1 and 3 from the output inductor to pins 45 and 46 on the IRPS5401 Figure 31 Current Sense Routing 5 3 VSENSE FEEDBACK In this screen gra...

Page 25: ...ith DB295 and DB296 demo boards Figure 32 VSENSE on layers 1 3 5 4 VIN Decoupling This screen grab shows that MLCC caps are placed directly aside the TDA21240 to create the shortest loop possible for...

Page 26: ...to SW D will be NAK s and a CML fault will be issued VIN_C and VIN_D must be connected to the same INPUT VOLTAGE Figure 34 Device operating mode example 6 1 Current Balance In C D Mode a phase balance...

Page 27: ...file access the PROGMAX register 4 in CNFG section must be 0 or 1 Both values indicate a single file is programmed Check User click Check MTP Left and finally click Program button The device will pro...

Page 28: ...MIC configuration stored within the multiple config file can be accessed by a resistor connected to the MTP pin The resistor must be connected from MTP to AGND pin 50 The resistor must be decoupled wi...

Page 29: ...shows 15 possible selections with an offset of 0 to an offset of 14 READ ONLY register 0x0052 11 8 nvm_user_image_sel shows the value of the offset given the resistor attached provided that the PROGMA...

Page 30: ...istor value point to an offset segment that was not programmed ANSWER No valid USER image will be loaded and the device will not start READ ONLY register 0x0052 12 nvm_read_no_image will be set to a 1...

Page 31: ...code LC Filter ADC Gain 256 Vin Ki Kp s 1 2 s pole LPF PI Controller G s Modulator VComp Vout Vref Duty cycle Vin Vref Figure 39 Emulator The output of the ADC is filtered by the low pass filter LPF a...

Page 32: ...eir application VIN VOUT FSW Inductor and Capacitor etc The tool will use the design inputs to calculate the minimum L and C Shown is a 1 V output at 800 kHz The calculated L for 33 ripple is 0 87 H A...

Page 33: ...ser guide with DB295 and DB296 demo boards The Compensator Tab contains the settings for Kpwm KPole and Fo crossover frequency Figure 42 Compensator tab The bode plot will be displayed when the Kp reg...

Page 34: ...34 of 63 V 1 2 2018 12 12 5 Output PMIC Controller IRPS5401 User guide with DB295 and DB296 demo boards 8 2 Recommended Circuit and Operating Parameters for Internal Switchers from the Data Sheet Fig...

Page 35: ...OUT L value L DCR L core loss and Switching Frequency Click on the Efficiency Sweep button Figure 45 Efficiency tool The tool will sweep the load from 0 A to the max IOUT specified The GUI will displa...

Page 36: ...roller IRPS5401 User guide with DB295 and DB296 demo boards The GUI will also display Figure 47 Percentage of output power contributed by each output Figure 48 Percentage of the total loss contributed...

Page 37: ...The LDO was not loaded for this test TEST SETUP The DB296 is mounted vertically with no forced airflow Ambient temperature is 25 C Figure 50 Test set up Table 4 Load conditions Output power SW A 1 997...

Page 38: ...losses calculated from Coiltronic website http www coilcraft com xal60xx cfm and http www coilcraft com xal4000 cfm Figure 52 Total inductor losses on SWITCHER C and D The inductors used in the 5 V C...

Page 39: ...at is being transferred to and dissipated in the copper of the PCB so the junction temperature and case temperature are essentially the same The 1st IR image shows that the case in the area of C D FET...

Page 40: ...Application Note 40 of 63 V 1 2 2018 12 12 5 Output PMIC Controller IRPS5401 User guide with DB295 and DB296 demo boards Figure 55 Thermal image of entire board...

Page 41: ...e DB295 6 will produce 5 outputs There are resistor stuff options that allow VCC to be connected to an external 5 V so the VIN pins can be used down to 1 2 V There is a resistor stuffing option at eac...

Page 42: ...s DB295 is designed to tie them to 5V signals For evaluation purposes this has not been a problem However in actual designs the datasheet of TDA2124x parts needs to be obeyed DB295 can be reworked to...

Page 43: ...Application Note 43 of 63 V 1 2 2018 12 12 5 Output PMIC Controller IRPS5401 User guide with DB295 and DB296 demo boards Figure 57 DB296...

Page 44: ...Application Note 44 of 63 V 1 2 2018 12 12 5 Output PMIC Controller IRPS5401 User guide with DB295 and DB296 demo boards Figure 58 DB296 schematic SW A internal FETs...

Page 45: ...Application Note 45 of 63 V 1 2 2018 12 12 5 Output PMIC Controller IRPS5401 User guide with DB295 and DB296 demo boards Figure 59 DB295 schematic SW A external FETs...

Page 46: ...respective regulation loop for SWA it is FB to RTN Values between 0 1uF and 2 2uF will deliver best results dependent on the board design Ground routing a If having more than one IRPS5401 in the syste...

Page 47: ...ormance data obtained from DB296 and DB295 with IR3555 as PowerStage SW A 1 0 V 100 mA 500mV div TON_RISE 1 msec Output Filter 1 H 7 22 F SW B 1 2 V 100 mA 500 mV div TON_RISE 1 msec Output Filter 1 H...

Page 48: ...th DB295 and DB296 demo boards Figure 60 Start up SW A 1 0 V 2 A 10 mV div 12 mVp p Output Filter 1 H 7 22 F SW B 1 2 V 2 A 10 mV div 13 mVp p Output Filter 1 H 7 22 F SW C 1 8 V 4 A 10 mV div 15 mVp...

Page 49: ...Application Note 49 of 63 V 1 2 2018 12 12 5 Output PMIC Controller IRPS5401 User guide with DB295 and DB296 demo boards Figure 61 Output ripple...

Page 50: ...10m V div 1 8 droop Output Filter 1 H 7 22 F P 35 I 42 Kpwm 3 Kpole 6 SW B 1 2 V 1 A Step 10 mV div 1 6 droop Output Filter 1 H 7 22 F P 36 I 43 Kpwm 3 Kpole 6 SW C 1 8 V 1 A Step 20 mV div 2 Droop Ou...

Page 51: ...PM 59 Output Filter 1 H 7 22 F P 35 I 42 Kpwm 3 Kpole 6 SW B 1 2 V 1 A Fco 55 kHz PM 59 Output Filter 1 H 7 22 F P 36 I 43 Kpwm 3 Kpole 6 SW C 1 8 V 2 A Fco 63 kHz PM 55 Output Filter 3 3 H 3 22 F P 4...

Page 52: ...Application Note 52 of 63 V 1 2 2018 12 12 5 Output PMIC Controller IRPS5401 User guide with DB295 and DB296 demo boards Figure 63 Bode plots...

Page 53: ...F P 35 I 42 Kpwm 3 Kpole 6 SW B 1 2 V 2 A 2 V div Vpeak 12 6 V Jitter 11 nsec Output Filter 1 H 7 22 F P 36 I 43 Kpwm 3 Kpole 6 SW C 1 8 V 4 A 2 V div Vpeak 12 7 V Jitter 57 nsec Output Filter 3 3 H 3...

Page 54: ...F P 35 I 42 Kpwm 3 Kpole 6 SW B 1 2 V 0 A 2 V div Vpeak 14 0 V Jitter 18 nsec Output Filter 1 H 7 22 F P 36 I 43 Kpwm 3 Kpole 6 SW C 1 8 V 0 A 2 V div Vpeak 13 1 V Jitter 48 nsec Output Filter 3 3 H 3...

Page 55: ...cation Note 55 of 63 V 1 2 2018 12 12 5 Output PMIC Controller IRPS5401 User guide with DB295 and DB296 demo boards EXT SW A DB295 GREEN VOUT Figure 66 Output ripple VIN 12 V VOUT 1 V Load 40 A fsw 50...

Page 56: ...tion Note 56 of 63 V 1 2 2018 12 12 5 Output PMIC Controller IRPS5401 User guide with DB295 and DB296 demo boards BLUE IOUT GREEN VOUT Figure 67 Mini slammer 5 A pulse 250 A sec with 20 A DC load 2kHz...

Page 57: ...te 57 of 63 V 1 2 2018 12 12 5 Output PMIC Controller IRPS5401 User guide with DB295 and DB296 demo boards BLUE IOUT GREEN VOUT CYAN SW NODE Figure 68 Load REP RATE 500 kHz 50 DC 500 kHz fsw 1400 Hz b...

Page 58: ...12 5 Output PMIC Controller IRPS5401 User guide with DB295 and DB296 demo boards Zoom in on MAX Peak to Peak Ripple The SW NODE pulse occurs at the end of the MAX load time BLUE IOUT GREEN VOUT CYAN S...

Page 59: ...AN SW NODE Figure 70 Min peak to peak ripple Efficiency of IRPS5401 IR3555 IRPS5401 in C D mode with VOUT_COMMAND 3 3 V and load set to 8 A SW_A set to 1 V with 40 A load Total Input Power is 78 48 W...

Page 60: ...1 TDA21240 IRPS5401 with TDA21240 including PCB inductor and capacitor loss Peak Peak efficiency Max Load Efficiency at maximum load current of 40A no VCC Efficiency not taking bias for TDA21240 and I...

Page 61: ...ds Revision history Document version Date of release Description of changes 1 0 Initial release 1 1 2018 09 10 Schematic updates restriction removed chapters 8 and 13 removed 1 2 2018 12 11 Schematic...

Page 62: ...Application Note 62 of 63 V 1 2 2018 12 12 5 Output PMIC Controller IRPS5401 User guide with DB295 and DB296 demo boards...

Page 63: ...tellectual property rights of any third party with respect to any and all information given in this application note The data contained in this document is exclusively intended for technically trained...

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