Application Note
14 of 63
V 1.2
2018-12-12
5 Output PMIC Controller/ IRPS5401
User guide with DB295 and DB296 demo boards
Figure 17
Inductor_ni_thresh
de_off_time_adj is an adjustment to the calculated LS FET on time. This prevents the inductor current from
going negative due to delays from the driver entering tri-state. Usually set to 6
400 nsec.
Figure 18
De_off_time_adj
**NOTE: IOUT reporting during AOT is not accurate. Do not send READ_IOUT commands while in AOT
Mode
4.3
External Sync
The IRPS5401 has a sync input (pin 52) that can be used to set the FSW to an external clock. The threshold
levels are LVTTL, 0.8V max for low and 2.1V min for high. The FSW setting for the IRPS5401 must be within a +/-
6.5% window of the desired sync frequency. The Sync input signal should be a 3.3V square wave with a 50%
duty cycle (+/- 10%)
** NOTE: Using external sync will cause a ~40 nsec ‘jitter’ on the SW_NODE when compared to no sync input but
it is not reflected in the VOUT ripple. See comparison below
Figure 19
TOP
SYNC in, MIDDLE
SW_NODE, BOTTOM
RIPPLE
