Application Note
15 of 63
V 1.2
2018-12-12
5 Output PMIC Controller/ IRPS5401
User guide with DB295 and DB296 demo boards
Figure 20
MIDDLE
SW_NODE, BOTTOM
RIPPLE
4.4
Current Sense and Over Current Settings
The 4 internal switchers sense IOUT by sensing the drop across the Rdson of the LS FET in the middle of the LS
FET conduction time. This gives the cleanest (least noisy) measurement because the SW_NODE has had time to
settle and stop ringing. Because the current is sensed in the middle of the LS FET on time (also the middle of
the inductor current down slope), the IRPS5401 senses the average output current, not the peak inductor
current.
The setting of the OC_WARN_LIMIT and OC_FAULT_LIMIT can be set to the DC value the user wants to see and
does not have to account for any added peak inductor current.
The OC_WARN_LIMIT is based on the output of the ADC and is filtered to 72 kHz. This digital current sense is
trimmed at ATE test to have a gain error of less than 5% and an offset error of less than 1% of the full load
capability.
The OC_FAULT_LIMIT is based on the output of a comparator that is looking directly at the Rdson. To ensure
OC_FAULT_LIMIT accuracy, the comparator is trimmed during ATE Test to tolerances of +/-10% at 3 A for the 2 A
outputs and +/-10% at 6 A for the 4 A outputs.
The PMBus commands OC_WARN_LIMIT and OC_FAULT_LIMIT have a range of 0 A to 15.97 A in increments of
31.25 mA. This means that the user can send a command and the IRPS5401 will ACK the command as valid.
However, the OC_FAULT_LIMIT is actually based on the comparator input which can only be set from 0 A to 4 A
in 0.25 A increments for the 2 A output and from 0 A to 8 A in 0.5 A increments for the 4 A outputs. (0 A to 16 A
for the combined C+D output) The internal logic will take the user’s commanded value and round it up to the
next real comparator setting. The OC_WARN_LIMIT is based on the ADC output so it really has 31.25 mA
increments. But it doesn’t make sense to set it above the OC_FAULT_LIMIT so it also has a practical limitation
of less than 15.97 A (except for the C+D application).
The user is encouraged to take into account the increase in inductor current that will occur during VOUT
increases. This capacitor charging current will have a magnitude of i= C_out*dv/dt and will be added to the DC
load current.
