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Design guide IDP2303(A)

Usage of dpVision

Application Note

Revision 2.0

2017-05-03

Parameter symbol

Parameter description

Default

Range

Unit

Slope

_TCO_init

LLC initial slope during soft start

0.85

0.0157 ~ 3.984 µs/0.5 ms

Slope

_TCO_min

LLC min slope during soft start

0.36

0.0157 ~ 3.984 µs/0.5 ms

_burst_sstart

LLC soft start steps

1 ~ 218

_burst_sstop

LLC soft stop steps

1 ~ 218

_burst_on_max

160

Slope

_burst_leave

LLC slope of soft start when
leaving burst mode

HBFB

0.32

0.0157 ~ 3.984 µs/0.5 ms

High_limit
Burst_off_time

High limit of burst off time for
adaptive minimum frequency
during burst on

120

20 ~ 200

Refer to 5.4.6 for limits

Summary of Contents for IDP2303

Page 1: ...Introduction 4 2 1 IC Introduction 4 2 2 Pin configuration and description 4 2 3 Product highlights 5 2 4 Application 6 3 PFC design 7 3 1 Target specifications 7 3 2 Power stage 7 3 2 1 Bridge rectif...

Page 2: ...heavy load 32 4 3 2 Current sense and OCP 32 4 3 3 Dead time 33 4 3 4 LLC model and regulation loop 33 4 3 4 1 LLC small signal model 33 4 3 4 2 VCO modeling 33 4 3 4 3 LLC regulation loop 34 5 Genera...

Page 3: ...l as the settings for parameters associated with general functions and protection features Useful tips on PCB layout are included to help the customers optimize their PCB design Lastly the installatio...

Page 4: ...rameters that help to ease the design in phase of the project 1 2 2 2 Pin configuration and description The pin configuration is shown in Figure 1 and Table 1 Figure 1 Pin configuration Table 1 Pin de...

Page 5: ...ridge current sense Pin CS1 is connected to an external shunt resistor and the source of the PowerMOS in the half bridge stage GD1 LSGD 12 O Gate driver output 1 half bridge low side gate driver Outpu...

Page 6: ...GND HV VAC ZCD VS CS0 Configuration HBFB Vout_2 MFIO Vout_1 STANDBY GD0 GD1 Figure 2 Typical application circuit for a power supply with IDP2303 HSGND HSVCC HSGD GD1 IDP2303A VCC GND 85 265 VAC CS1 Z...

Page 7: ...at 90 VAC sys 87 Estimated efficiency of PFC at 90 VAC PFC 93 Estimated efficiency of PFC at 265 VAC PFC_265 96 Minimum switching frequency fsw_min 25 kHz Power factor 0 9 3 2 Power stage A simplified...

Page 8: ...characteristics With the CE in 500 V E6 and P6 family in 600 V Infineon offers various series with extremely low conduction and switching losses that can make switching applications more efficient mor...

Page 9: ...plications Vgate_high up to VCC possible rail to rail operation Figure 5 Gate drive concept 3 2 3 2 Gate drive stability Due to the unique gate drive with configurable charge current and regulated gat...

Page 10: ...atively slow for better EMI performance Apart from the gate drive resistance itself 10 k resistors R5 and R6 are also commonly connected between MOSFET gate and source to help damping some overshoot a...

Page 11: ...the frequency law or when the ZCD signal is too weak to be detected within 40 us The second condition will not affect the design of inductor Figure 7 illustrates the inductor current and timing durin...

Page 12: ...mum current defined by OCP and not become saturated Otherwise a large current will result from the saturation and potentially damage devices if it is present for some time 3 3 Control parameters and p...

Page 13: ...ode operation If the average sensed PFC bus voltage falls below a configurable UVP threshold for a blanking time then PFC under voltage is detected As a result PFC and LLC will stop switching immediat...

Page 14: ...IC is always active and the PFC and or LLC switch continuously so the voltage divider is always in circuit However the conduction loss is only a very small portion of the total loss With the IDP2303...

Page 15: ...voltage Thus the clamping current can be calculated as Negative clamping current _ _ Positive clamping current _ _ _ For example with a turn ratio of 8 diode forward voltage drop of 0 7V each and mini...

Page 16: ...g edge 1 2 V range tCSOCP1 20 320 620 ns 1 input signal slope dVCS dt 10 mV s 2 90 170 250 ns 1 input signal slope dVCS dt 150 mV s 2 90 140 210 ns 1 input signal slope dVCS dt 300 mV s 2 1 Not tested...

Page 17: ...esign guide IDP2303 A PFC design Application Note 17 Revision 2 0 2017 05 03 A spradsheet based calculation example for selecting the current sense resistor and the OCP tolerance is shown in Figure 12...

Page 18: ...Design guide IDP2303 A PFC design Application Note 18 Revision 2 0 2017 05 03 Figure 12 Accurate calculation of OCP tolerance...

Page 19: ...6 7 200 39 99 0 34 This value is less than the saturation magnetic flux density B of 0 35 T PC40 magnetic material Therefore the PFC choke will not saturate under worst case conditions 3 3 5 Frequenc...

Page 20: ...tw t t Figure 13 Current and timing in QR2 operation 3 3 5 2 Frequency law A frequency law consisting of a maximum switching frequency and the minimum switching frequency is defined for the valley se...

Page 21: ...the switching frequency must increase by reducing the QRN When the switching frequency reaches the maximum frequency the frequency law defines that the frequency is too high and switching frequency mu...

Page 22: ...unt resistor as shown in Figure 15 The internal shunt resistor RHV shunt set to 125 internal 500 series resistor and the external RHV resistors to save design effort a value of 51k with 1 tolerance is...

Page 23: ..._24 3 5 A Output voltage Vo_12 12 V Output current Io_12 3 A Output power Po_LLC 120 W LLC efficiency LLC 93 Resonant frequency fr 100 kHz Hold up time thold 20 ms 4 2 Power stage A simplified applica...

Page 24: ...turns ratio is less than the physical turns ratio due to the leakage inductance in the transformer secondary The equivalent turns ratio can be estimated as where 1 is the ratio between the primary in...

Page 25: ...t in Figure 18 that can be derived with the First Harmonic Approximation FHA modelling methodology Figure 18 Equivalent circuit If the total output load is referred to 24 V the effective load resistan...

Page 26: ...ign must be re calculated as 1 2 0 74 1 2 2 1 2 100 103 2 10 10 9 253 1 1 The value of can be achieved by adjusting the gap length From the gain curve with 0 74 in Figure 19 the normalized frequency 0...

Page 27: ...is selected to avoid magnetic saturation Then can be calculated at minimum bus voltage _ by 2 7 5 24 0 5 2 87 10 3 88 10 6 0 62 20 The selection of the number of turns on the primary side must also ta...

Page 28: ...ct on the shape of gain curves and the attainable maximum gain Larger values of result in flatter gain curves which leads to a wider operation frequency range In the real world the selection of is als...

Page 29: ...d as below The maximum drain current through the MOSFET is the same as that through the resonant capacitor 2_ _ 0 89 2_ 2 0 892 2 5 1 98 2 5 is the on state resistance of MOSFET at junction temperatur...

Page 30: ...requency fHB based on the average LLC feedback voltage VHBFB With a DPdigital controller a VCO curve based on switching period can be easily implemented digitally The curve of the LLC switching period...

Page 31: ...ined by the hardware configuration For example the IDP230x IO pullup voltage range is 0 3 3 V and the ADC range is 0 2 4 V thus the full VCO range should be within 0 2 4 V 4 3 1 2 _ and _ The frequenc...

Page 32: ...uctance and 3 5 for the resonant capacitance Additional equivalent voltage drops caused by the transformer winding and PCB traces will affect the actual voltage gain Usually the transformer internal v...

Page 33: ...ns During the LLC converter s switching dead time the magnetizing current charges or discharges the switching node to achieve ZVS The relevant capacitance at the switch node is the sum of the transist...

Page 34: ...he LLC regulation loop is based on external analog circuits and is controlled by the TL431 regulation network The configuration is shown in Figure 22 below Figure 22 Analog control loop configuration...

Page 35: ...ction is 0 1 1 1 1 0 1 0 0 2 1 2 1 1 1 There are 2 zeros 2 poles and an origin pole some of which are coupled to each other The resistance and capacitance are also limited by the physical circuit cons...

Page 36: ...up cell depletion MOS normally on device is switched on during the VCC startup phase when the IC is inactive A current flows from the HV pin to the VCC pin via an internal diode which charges the capa...

Page 37: ...es active and before the LLC starts to supply the VCC voltage To meet the first criteria _ 90_ 1 20 5 90 2 2 51 7 1 20 5 1 57 1 20 5 76 51 0 7 51 7 The value of VCC_ON can be found in the datasheet is...

Page 38: ...HV pin occurs the AC voltage may be at a much lower value then the Y capacitor will be discharged through all possible discharge paths and thus causes spikes in the touch current This spike current ma...

Page 39: ...one bit of 0 the following first byte can be read which indicates the state of the gearbox usually protection information Figure 25 Example of black box function OCP1 As an example the digital informa...

Page 40: ...CC GND current sense GND MOSFET diode heatsink and EMI return GND shall all be star connected to the PFC bulk capacitor ground directly and the PCB traces should be as short as possible The second gro...

Page 41: ...ZCD pin and IC GND pin This trace shall be kept far away from the LLC high side driver circuit including the high side GND pin to avoid high dv dt coupling The two PCB traces from the PFC choke auxil...

Page 42: ...s possible so that the radiated EMI noise can be effectively reduced 6 7 Passing 4 kV lightning surge test To pass the 4 kV lightning surge test PCB spark gaps or spark gap devices across the input co...

Page 43: ...possible mutual interference the HBFB and PFC ZCD signal related PCB traces shall not be close or in parallel to the HV pin related PCB traces and LLC main current loop Any PCB track carrying a high c...

Page 44: ..._addon_generator msi file 3 Step 2 above will copy and paste documents images parameters to C Users Login Infineon Technologies AG dp vision 4 Connect the dpIFGen2 interface board using the USB cable...

Page 45: ...uld turn green Figure 35 Power device On Off button and device status 9 Press the Test configuration set button so that parameter values are loaded into the IDP230x sample and application firmware sta...

Page 46: ...t break time 2 s t_VCCOVP VCC OVP blanking time 9 ms Table 9 PFC parameters Parameter symbol Parameter description Pin Default Range Unit V_GD0H 1 PFC GD0 drive voltage GD0 10 5 4 5 15 V I_GD0H 1 PFC...

Page 47: ...FB 2 0 1 2 3 V V_HLVCO LLC VCO heavy load voltage HBFB 2 0 1 2 3 V V_LLVCO LLC VCO light load voltage HBFB 0 45 0 1 2 3 V f_MaxVCO LLC VCO max frequency 250 1 300 kHz f_LLVCO LLC VCO light load freque...

Page 48: ...Slope_TCO_min LLC min slope during soft start 0 36 0 0157 3 984 s 0 5 ms N_burst_sstart LLC soft start steps 4 1 218 N_burst_sstop LLC soft stop steps 4 1 218 T_burst_on_max 160 us Slope_burst_leave...

Page 49: ...21 3 Infineon Technologies CrCM Boost PFC Converter Design Design Note DN 2013 10 V1 0 January 2013 4 Infineon Technologies Primary Side MOSFET Selection for LLC Topology Application note V1 0 June 2...

Page 50: ...ect to such application For further information on the product technology delivery terms and conditions and prices please contact your nearest Infineon Technologies office www infineon com WARNINGS Du...

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