Infineon CoolGaN Manual Download Page 6

  

Application Note 

6 of 23 

V 1.1  

                                                                                                                                                                                                                                                                     2020-11-09  

CoolGaN™ 600 V half-bridge evaluation platform featuring GaN 
EiceDRIVER™ 

  

Circuit description 

   

The TNEG pins of U1 and U2 are connected to timing resistors R13 and R23 respectively. These resistors 
program the duration of the negative off voltage as explained in section 3.7 of the 

1EDF5673K datasheet

. If you 

adjust the deadtime to longer than 100 ns, then R13 and R23 should be proportionally increased to ensure that 
the negative gate voltage duration t

neg

 is always longer than the programmed deadtime. C18 and C28 are for an 

earlier version of the driver IC and are not required, so are not populated on the PCB. 

The 5 V input power (VDDI) to the two gate driver ICs is bypassed with a 22 nF high-frequency bypass capacitor 
(Cx2), along with a 470 Ω resistor. This is per the recommendation in the gate driver datasheet to properly bias 
the built-in 3.3 V shunt regulator. 

Note:

 

If the PWM frequency is expected to exceed 1 MHz, then R12 and R22 should be reduced from 470 

Ω

 

to 390 

Ω

. Otherwise there may not be sufficient current to maintain 3.3 V regulator bias. 

3.2

 

Isolated gate driver power supply 

Power for the gate drivers is provided by a simple isolated DC-DC converter shown i

Figure 5

It takes the +5 V 

input and provides two isolated 8 V outputs (VDD1-VSS1, and VDD2-VSS2). A small transformer T1 provides low-
capacitance isolation and voltage scaling. The primary of T1 is driven by U31, a MAX256 isolated power supply 
driver. It provides 50 percent duty-cycle PWM, current-limited, balanced voltage to the transformer at about 
500 kHz. The secondary sides are both voltage doublers consisting of Dx2, Dx3, Cx5, and Cx6. The voltage 
doublers are used instead of straight rectifiers because this reduces the transformer turns ratio, thus providing 
lower leakage inductance for better load regulation. A small green LED Dx4 provides a visible indication that 
both high and low-side bias supplies are functioning. 

 

 

Figure 5

 

Isolated gate driver power supply 

3.2.1

 

Gate driver power supply transformer 

The transformer used in the gate driver power supply is specifically designed to operate with the driver IC U31 
(i

Figure 5

at 500 kHz, with the appropriate turns ratio to provide the twin isolated 8 V outputs with the 

doubler circuit. Moreover, the winding arrangement balances low inter-winding capacitance with good 
coupling (low leakage inductance) and >1000 V isolation. The low capacitance (<2 pF) is important for 
minimizing common-mode current injection due to fast switching transients, and the low leakage helps with 
open-loop output voltage regulation. 

 

Summary of Contents for CoolGaN

Page 1: ...of EiceDRIVER GaN gate drivers and isolated power supplies for the gate drivers along with input logic that provides adjustable deadtime Using an external inductor the board can be configured for buck...

Page 2: ...mer 6 3 3 Gate drive circuit 7 3 4 Half bridge output circuit 8 4 Setup and use 9 4 1 Test equipment needed 9 4 2 Connections to the terminal block 9 4 2 1 Connections for double pulse testing 10 4 2...

Page 3: ...range up to 450 V limited by the capacitor rating This half bridge can switch continuous currents of 12 A and peak currents of 35 A hard or soft switching Operating frequency can be up to several MHz...

Page 4: ...it Deadtime Circuit Isolated Gate Drive Power Vin Vo Vin PWM 0V Evaluation Board 0 400 V DC Laboratory Power Supply Test Inductor 5 V DC Laboratory Power Supply 50 Pulse Generator Figure 2 Evaluation...

Page 5: ...be set long enough that the high side always fully turns off before the low side turn on with some margin and vice versa A simple adjustable RCD delay circuit generates the deadtime Whenever U11 or U...

Page 6: ...DC DC converter shown in Figure 5 It takes the 5 V input and provides two isolated 8 V outputs VDD1 VSS1 and VDD2 VSS2 A small transformer T1 provides low capacitance isolation and voltage scaling Th...

Page 7: ...e gate RC network described in the datasheet consists of Rx4 Cx4 and Rx5 The small Schottky diode Dx5 provides a low impedance return path for faster gate turnoff effectively bypassing Rx4 Note that t...

Page 8: ...wer supply Attention Normally the bus capacitor is discharged when the lab power supply is switched off But if the power connector is removed while the capacitor is charged not recommended the bus cap...

Page 9: ...a conventional BNC connector you will need a BNC male to MMCX plug cable Fairview Microwave FMC0809315 or a BNC to MMCX adapter Oscilloscope for measurement Due to the fast transient voltage and curre...

Page 10: ...external inductor is connected between Vsw and Vo terminals the circuit is configured as a buck converter If a PWM signal is applied to the PWM input the output voltage will be proportional to the in...

Page 11: ...nductor 5 V DC Laboratory Power Supply 50 Pulse Generator DC Load Figure 9 Connecting the evaluation board in the buck topology Figure 10 shows example waveforms operating in ZVS buck mode at 1 5 MHz...

Page 12: ...V to zero there is a large change in Crss and thus a significant charge injected into the gate approximately 3 nC This charge in a short time I dq dt results in a short current spike that pulls the ga...

Page 13: ...this signal is delayed from TP4 by the deadtime circuit so it has an exponential risetime characteristic Voltage level is standard 5 V AHCT logic level TP1 High side gate voltage signal is the gate of...

Page 14: ...e rising edge of PWM To verify and adjust deadtime connect a 5 V DC supply to the 5 V input on the eval board and connect a pulse generator to the PWM input J1 refer to section 4 3 Set the generator f...

Page 15: ...ly the rising and falling edge deadtimes are set to the same value Turning the trimpots clockwise increases the deadtime Figure 13 Measuring deadtime on the falling edge of PWM 4 7 Test inductor recom...

Page 16: ...zero reverse recovery characteristic Double pulse testing is typically done 1 burst at a time not continuously in order to keep power dissipation low even when testing to the voltage and current limit...

Page 17: ...gh side transistor operating in 3rd quardrant conduction mode You can see the switch node voltage rises several volts above the bus during deadtime due to the effective diode drop across the high side...

Page 18: ...form featuring GaN EiceDRIVER Complete schematic 5 Complete schematic Note Part numbers 1 9 are in the ouput power stage 1x part numbers belong to the high side gate drive 2x are low side gate drive a...

Page 19: ...ng GaN EiceDRIVER PCB layout 6 PCB layout The evaluation board is 1 6 mm thick with 4 evenly spaced copper layers 35 m thick The layer stackup is depicted below Figure 16 Top layer copper layer with t...

Page 20: ...11 09 CoolGaN 600 V half bridge evaluation platform featuring GaN EiceDRIVER PCB layout Figure 18 Lower middle copper layer with top and bottom component overlay Figure 19 Bottom copper layer with bot...

Page 21: ...3 D14 D24 LED GREEN CLEAR 0805 SMD J1 CONN MMCX JACK STR 50 OHM SMD Q1 Q2 Infineon IGOT60R070D1 CoolGaN Transistor R1 R2 RES SMD 499K OHM 1 1W 2512 R11 R21 TRIMMER 1k OHM 0 125W SMD R12 R15 R22 R25 RE...

Page 22: ...aN EiceDRIVER Revision history 8 Revision history Document version Date of release Description of changes V 1 0 2019 01 16 First release V 1 1 2020 11 09 Updates for version B of the driver IC updated...

Page 23: ...intellectual property rights of any third party with respect to any and all information given in this application note The data contained in this document is exclusively intended for technically trai...

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