IFR FM/AM-500, Maintenance Manual

Page: 188 / 320

A second output of the frequency detector operates in the phase
lock indicator circuit. When the phase of the divider network
output differs from the phase of the reference signal, an LED
on the High Loop is illuminated and a logic voltage from the
Generate Audio Module is grounded, allowing that logic circuit
to produce a 2 Hz signal to the LOCK light on the Front Panel
rather than the normal steady DC. This causes the Front Panel
LED to flash at approximately half-second intervals.
B. RF FEEDBACK AMPLIFIER CIRCUIT (On Divider PC Board)
The 90-1088 MHz feedback signal from the Dual VCO goes through
a four-stage amplifier consisting of amplifiers U4101, U4102
and U4103, and RF transistor Q4101. The output of the amplifier
is split, with one part going throug� a level-shaping network
consisting of choke L4105, resistor R4148 and capacitor C4158,
to the +4 prescaler U4104. The second part goes to an AGC cir­
cuit which feeds back to diode CR4110 between amplifiers U4102
and U4103, thus decreasing the signal level to amplifier U4103
as the forward-bias decreases. Diode CR4111 and capacitor
C4154 form a level detector, while potentiometer R4145 allows
adjustment of the AGC level. The output of op amp U4111, thus,
is positive when the signal is relatively weak, which turns on
diode CR4110 and allows the input to amplifier U4103 to
increase. This results in a stronger signal to op amp U4111.
When the signal strength is greater than the non-inverting
input, the output becomes more negative, which would increase
the signal flow at CR4110. However, capacitor C4155, which is
parallel with the op amp, prevents abrupt changes in the feed­
back signal and allows the op amp to-adjust the signal level to
equilibrium with the reference voltage on the non-inverting
input to the op amp.
C. FEEDBACK FREQUENCY DIVIDER (On Divider PC Board)
Prescaler U4104 (+4) divides the signal from the RF amplifier,
then sends it to prescaler U4107 (+5/+6). Counter U4105 fur­
nishes the signal to gate U4108B, which sets U4107 to divide by
six for a selected number of pulses, then by five until the end
of count is reached. Counter U4105 furnishes the signal which
sets U4107 to divide by six. Decade counters U4105, U4106 and
U4109 count the output pulses from U4107, starting with the
numbers set on the three left-most (l's, 10
1
s and 100
1
s MHz) RF
FREQUENCY Thumbwheels. When the end-of-count is reached, gates
U4108A and U4108C clock flip�flop U4110B, which resets the
counters and flip-flop U4110A. U4110A then provides the signals
to the ECL-to-TTL translator in prescaler U4107, which, in
turn, produces a squarewave at approximately 500 kHz.
D. SECOND FEEDBACK AMPLIFIER (On Analog PC Board)
The second feedback amplifier utilizes transistors Q4003 and
Q4004. Wh�n the feedback signal is high, Q4004 conducts,
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