IFR FM/AM-500, Maintenance Manual

Page: 209 / 320

7-9 DIGITAL MODULE
7-9-1 THEORY OF OPERATION (Refer to Figure 7-10 and Digital Counter
and Digital Reference Circuit Schematics in Section 10)
A. GENERAL
As a signal source, the Digital Module divides the 1 MHz refer­
ence signal from the Frequency Standard into frequencies of
10 Hz, 100 Hz, 1 kHz and 10 kHz. According to the Frequency
Error Range Switch position, one of these four frequencies is
applied to the frequency error counter system. In addition,
the 100 Hz signal is used as a reference signal by the Low Loop
Synthesizer and the 1 kHz signal is used for the fixed audio
tone and as a reference frequency for the 21.4 MHz VCO in the
Receiver/Generator Module. A 21.4 MHz sample from the VCO is
divided and compared with the 1 kHz by a phase comparator which
supplies a tuning voltage to the VCO.
As an RF frequency counter, a counter system counts the incoming
carrier signal digitally, and produces an analog voltage to
drive the Frequency Error Meter according to its difference
from a pre-set count. For audio frequency counting, the
counter system digitally compares the demodulated audio fre­
quency to the frequency set on the VAR TONE FREQ thumbwheels,
and produces a corresponding analog voltage.
The Digital Module is divided, for discussion purposes, into
three major circuits; the Frequency Divider Circuit, the Timing
Circuit, and the Counter System.
B. FREQUENCY DIVIDER CIRCUIT (On Digital Reference PC Board)
The incoming 1 MHz reference signal is divided successively by
BCD counters U4505, U4506 and U4507 to produce frequencies of
10 kHz, 1 kHz, 100 Hz and 10 Hz. These signals are all coupled
to time-base multiplexer U4508. In addition, the 100 Hz fre­
quency is fed to the Low Loop Synthesizer; the 1 kHz is the
reference for the 21.4 MHz VCO phase detector, and also goes to
a 1 kHz bandpass filter consisting of op amps U4514A, U4514B
and U4515A and related circuitry. The bandpass filter changes
the square wave into a sinewave for the 1 kHz fixed tone audio
signal. The 21.4 MHz VCO sample is first amplified by tran­
sistor Q4501, then divided by counters U4501 and U4502 and NANO
gate U4516 to produce a frequency of lkHz. PLL (Phase Locked
Loop) U4503 compares this frequency with the 1 kHz signal from
the time-base divider circuit and produces a VCO tuning voltage.
The potentiometer in the GEN/LOCK control on the Front Panel
provides an alternative VCO tuning voltage. The GEN/LOCK Con­
trol Switch applies approximately +5
voe
when in the GEN posi­
tion, enabling multiplexer U4504C to select between these two
alternative tuning voltages.
7-47