IFR FM/AM-500, Maintenance Manual

Page: 210 / 320

C. TIMING AND SIGNAL SELECTOR CIRCUIT (On Digital Counter PC Board)
In the timing circuit, counter U4411 divides the time-base fre­
quency by 10. Dual master-slave flip-flop U4412A and U4412B
provide timed control signals. Triple multipleier U4401A,
U4401B and U4401C provides signal selection. Dual one-shot
multivibrator U4413A and U4413B resets the system. A multiplier
circuit (installed on the Digital Reference PC Board) multiplies
the audio signal by a factor of 100 so it can be counted during
the established time-base period. The multiplier circuit con­
sists of demultiplexer U4509, PLL U4510 and counter U4511 for
the reference signal and PLL U4512-and counter U4513 for the.
unknown audio frequency.
In the audio frequency multiplier circuit, demultiplexer U4509
(on Digital Reference PC Board) selects the capacitance required
for timing the VCO in the PLL according to the setting of the
VAR TONE FREQ Thumbwheels. The output frequency of the PLL VCO
is sampled by the counter, and divided by 100. The PLL com­
parator compares the counter output frequency to the incoming
audio frequency (reference or unknown), and produces a VCO
tuning voltage which is used by the PLL VCO for its own tuning.
The output from each PLL is coupled to one input of multiplexer
U4401B.
The control signal for multiplexer U4401B is from the Q output
of slaved flip-flop U4412B. When this signal is low, U4401B
feeds the unknown audio frequency (multiplied by 100) to multi­
plexer U4401C. When the Q output is high, U4401B feeds the
reference signal (also multiplied by 100) to U4401C. When the
Frequency Error Range Switch on the Front Panel is in one of
the RF positions, multiplexer U4401C couples the demodulated
10.7 MHz carrier signal to the counter system. With the switch
in one of the AUDIO positions, the unknown and reference signals
(multiplied by 100) are selected.
According to the setting of the Frequency Error Range Switch,
the time-base selector U4508 feeds one of the four frequencies
available to it to counter U4411 for division by 10. The
counter's end-of-count signal clocks master flip-flop U4412A.
Starting with the condition of Q being high, when U4412A is
clocked by U4411, Q goes low and Q goes high. The Q signal
inhibits the counter system and is applied to multiplexer
U4401A as a reset signal. Through inverter U4421, the corres­
ponding low Q becomes high, clocking U4412B and resetting
counter U4411 to a count of 9. The next time-base pulse then
causes U4411 to again clock U4412A. Q goes low, Q goes high,
and the cycle repeats.
When the Q output from slaved flip-flop U4412B is low, the
counter system counts upward and multiplexer U4401B couples the
unknown audio signal to the signal selector multiplexer U4401C.
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