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Appendix A Watchdog Timer
The Watchdog Timer is a device to ensure that standalone systems can always
recover from catastrophic conditions that cause the CPU to crash. This condition
may have occurred by external EMI or a software bug. When the CPU stops
working normally, hardware on the board will perform hardware reset (cold boot)
to bring the system back to a known state.
Three I/O ports control the Watchdog Timer:
443
Write
Set Watchdog Time period
443 (hex)
Read
Enable the refresh the Watchdog Timer
043/843 (hex)
Read
Disable the Watchdog Timer
Prior to enable the Watchdog Timer, user has to define Timer first. The output
data is a value of time interval and the range of the value is from 01(hex) to FF
(hex) and time interval 1 sec to 255 sec.
DATA TIME
INTERVAL
01 1
sec
02 2
sec
03 3
sec
04 4
sec
- -
- -
FF 255
sec
This will enable and activate the countdown timer which eventually time out and
reset the CPU to ensure that this reset condition does not occur; the Watch-Dog
Timer must be periodically refreshed by reading the same I/O port 043/843H
and 443H. This must be done within the time out period that is selected by
software, please refer to the example program.
A tolerance of at least 5% must be maintained to avoid unknown routines within
the operating system (DOS), such as disk I/O that can be very time consuming.
Therefore if the time-out period has been set to 10 seconds, the I/O port 443H
must be read within 7 seconds.
Note: When exiting a program it is necessary to disable the Watchdog Timer,
otherwise the system will reset.
