IEI Technology Wafer-8522, User Manual

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WAFER-8522 Motherboard
3 Universal Host Controller Interface (UHCI) controllers
High-speed, full-speed and low-speed capable
2.6.6 Intel
®
ICH4 PCI Interface
The PCI interface on the ICH4 is compliant with the PCI Revision 2.2 implementation.
Some of the features of the PCI interface are listed below.
PCI Revision 2.2 compliant
33MHz
5V tolerant PCI signals (except PME#)
Integrated PCI arbiter supports up to six PCI bus masters
2.6.7 Intel
®
ICH4 Low Pin Count (LPC) Interface
The ICH4 LPC interface complies with the LPC 1.0 specifications. The LPC bus from the
ICH4 is connected to the following components:
BIOS chipset
Super I/O chipset
2.6.8 BIOS
The BIOS flash memory chip on the WAFER-8522 has a licensed copy of AMI BIOS
loaded onto it. The BIOS flash memory chip is connected to the chipset via the LPC bus.
The flash BIOS features are listed below:
SMIBIOS (DMI) compliant
Console redirection function support
PXE ( P re-Boot E x ecution E nvironment) support
USB booting support
2.7 PCI Bus Components
2.7.1 PCI Bus Overview
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