IEI Technology IOWA-MARK-533-128MB-R10, User Manual

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IOWA-MARK Half-size CPU Card
2.6 PCI Bus
2.6.1 Overview
The PCI bus provides a PCI interface between the VIA MARK and the VIA VT82C686B.
The PCI bus provides also provides a communication interface between the USB
connectors and the USB 1.1 controller on the VIA VT82C686B. The SATA drives and the
single RJ-45 Ethernet connector are also interfaced to the VIA MARK and VIA
VT82C686B through the PCI bus. Some of the features of the PCI bus are listed below:
33MHz Revision 2.3 is implemented
Up to six external bus masters are supported
Maximum throughput: 133MB/sec
Master devices: Maximum of six with three implemented
One PCI REQ/GNT pair can be given higher arbitration priority
44-bit addressing using the DAC protocol supported
2.6.2 10/100M Ethernet
A highly integrated and cost-effective single-chip, fast RealTek RTL8100C 10/100M
Ethernet controller is interfaced through first the PCI bus a to the CPU and system chipset.
The RealTek RTL8100C controller provides 10Mbps or 100Mbps Ethernet connectivity to
the IOWA-MARK. Some of the features of the RealTek RTL8100C are listed below.
10Mbps and 100Mbps operation
Supports 10Mbps and 100Mbps N-way auto-negotiation
Supports 25MHz Crystal or 25MHz OSC as the internal clock source
Complies with PC99/PC2001 standards
Supports ACPI power management
Provides PCI bus master data transfer
Provides PCI memory space or I/O space mapped data transfer
Supports PCI clock speed of 16.75MHz-40MHz
Advanced power saving mode
Supports Wake-on-LAN and remote wake-up (AMD Magic Packet™, Link
Change, and Microsoft® Wake-up frame)