High-speed Multifunction Boards
User Manual, Ver. 1.0, May 2015, PMH-029-10 Page 47
6.2
I/O Address Mapping
An overview of the registers for the PCIe-8620/8622 Series board is given below. The address of
each register can be determined by simply adding the offset value to the base address of the
corresponding Bar number. More detailed descriptions of each register can be found in the
following.
Bar No.
Offset
Register Function Description
Read
Write
0
(MMIO)
00H
Read AI FIFO Data
N/A
04H
AI FIFO Status
Clear FIFO
08H
Internal Clock Control/Status
Internal Clock Control/Status
0CH
AI Mode Control/Status
AI Mode Control/Status
10H
Read AI Data
AI Trigger
14H
Read AI Data
Start AI Trigger
18H
Interrupt Control/Status
Interrupt Control/Status
1CH
N/A
Clear Interrupt
20H
AO Control/Status
AO Control/Status
24H
Read DI Port and DO Port status
Write DO Port
28H
Counter 0 Control/Status
Counter 0 Control/Status
2CH
Counter 0 Period Control/Status
Counter 0 Period Control/Status
30H
Counter 1 Control/Status
Counter 1 Control/Status
34H
Counter 1 Period Control/Status
Counter 1 Period Control/Status
3CH
Read Card ID and firmware Version
N/A
1
(MMIO)
00H
∣
40H
Xilinx Spartan-6 DMA Control/Status Xilinx Spartan-6 DMA Control/Status
Note: The length of the register is 32-bits.
