High-speed Multifunction Boards
User Manual, Ver. 1.0, May 2015, PMH-029-10 Page 3
5
TESTING THE PCIE-8620/8622 SERIES BOARD ...................................................................................................... 36
5.1
PCI
E
-8620
S
ELF
-T
EST
........................................................................................................................................... 36
5.2
PCI
E
-8622
S
ELF
-T
EST
........................................................................................................................................... 41
6
I/O REGISTER ADDRESSES ................................................................................................................................... 46
6.1
H
ARDWARE
ID ..................................................................................................................................................... 46
6.2
I/O
A
DDRESS
M
APPING
......................................................................................................................................... 47
6.3
B
AR
0
(MMIO) ................................................................................................................................................... 48
6.3.1
Interrupt and Initialize Control/Status Registers ......................................................................................... 48
6.3.2
Digital I/O Registers .................................................................................................................................... 50
6.3.3
Analog Input Registers ................................................................................................................................ 51
6.3.4
Analog Output Registers ............................................................................................................................. 53
6.3.5
Counter Registers ........................................................................................................................................ 54
6.4
B
AR
1
(MMIO) ................................................................................................................................................... 55
6.4.1
Xilinx Spartan-6 Control/Status Registers ................................................................................................... 55
7
CALIBRATION .................................................................................................................................................... 56
7.1
I
NTRODUCTION
..................................................................................................................................................... 56
7.2
S
TEP
-
BY
-S
TEP
C
ALIBRATION
P
ROCESS
........................................................................................................................ 58
7.2.1
PCIe-8622 Calibration Step .......................................................................................................................... 58
7.2.2
PCIe-8620 Calibration Step .......................................................................................................................... 80
8
WINDOWS API FUNCTION ................................................................................................................................ 90
APPENDIX: DAUGHTER BOARDS .................................................................................................................................. 91
DN-68A ........................................................................................................................................................................... 91
DN-25 ............................................................................................................................................................................. 92