PCI-1202/1602/180x Series Card
Multi-Function Boards
User Manual/ Ver. 4.8/ Mar. 2015/ PMH-0014-48/ Page: 55
6.4
BAR1: Timer Control
The timer-0 is used as the internal A/D pacer trigger. The timer-1 is designed for the A/D pacer
trigger in the external trigger mode. The timer-2 is used as the machine independent timer.
The
timer-2 is very important for settling time delay.
Refer to Intel’s “Microsystem Components
Handbook” for 8254 programming. The block diagram of the 8254 timer is given as follows:
Figure 6.4-1: The Block diagram of 8254 timer for the PEX-1202/PCI-1202/1602/180x series.
CLK
Timer 0
OUT0
CLK
Timer 1
OUT1
CLK
Timer 2
OUT2
8Mhz
Local Data Bus
Internal Pacer timer
External Pacer timer
ADC
Machine indenpedent Timer
D0,D1 ... D7
The I/O address of 8254 timer is given as follows:
I/O address of timer/counter_0
wAd0 *4
I/O address of timer/counter_1
wAd1 *4
I/O address of timer/counter_2
wAd2 *4
I/O address of control register
wAd3 *4
